sin3.vhd

来自「《CPLD_FPGA设计及应用》课件与实例」· VHDL 代码 · 共 61 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY sin3 IS
  PORT(clk:IN STD_LOGIC;
       datain:IN STD_LOGIC;
       mclk:IN STD_LOGIC;
       sel:IN STD_LOGIC_VECTOR(1 DOWNTO 0);
       ad:OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
       aout:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
       bout:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
       cout:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END sin3;
ARCHITECTURE sin3generator OF sin3 IS
  COMPONENT controller 
    PORT(clk:IN STD_LOGIC;
         datain:IN STD_LOGIC;
         ad:OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
         freq:OUT STD_LOGIC_VECTOR(15 DOWNTO 0));
  END COMPONENT; 
  COMPONENT clkdiv 
    PORT(mclk:IN STD_LOGIC;
         freq:IN STD_LOGIC_VECTOR(15 DOWNTO 0);
         clkout:OUT STD_LOGIC);
  END COMPONENT; 
  COMPONENT addresscounter 
    PORT(clk:IN STD_LOGIC;
         address:OUT STD_LOGIC_VECTOR(8 DOWNTO 0));
  END COMPONENT; 
  COMPONENT mod360  
    PORT(address:IN STD_LOGIC_VECTOR(8 DOWNTO 0);
         addressout:OUT STD_LOGIC_VECTOR(8 DOWNTO 0));
  END COMPONENT; 
  COMPONENT rom  
    PORT(address:IN STD_LOGIC_VECTOR(8 DOWNTO 0);
         sel:IN STD_LOGIC_VECTOR(1 DOWNTO 0);
         data:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
  END COMPONENT; 
  SIGNAL freq:STD_LOGIC_VECTOR(15 DOWNTO 0);
  SIGNAL clkout:STD_LOGIC;
  SIGNAL address1:STD_LOGIC_VECTOR(8 DOWNTO 0);
  SIGNAL address2:STD_LOGIC_VECTOR(8 DOWNTO 0);
  SIGNAL address3:STD_LOGIC_VECTOR(8 DOWNTO 0);
BEGIN
  U1:controller
     PORT MAP(clk,datain,ad,freq);
  U2:clkdiv
     PORT MAP(mclk,freq,clkout);
  U3:addresscounter
     PORT MAP(clkout,address1);
  U4:mod360
     PORT MAP(address1,address2);
  U5:mod360
     PORT MAP(address2,address3);
  U6:rom
     PORT MAP(address1,sel,aout);
  U7:rom
     PORT MAP(address2,sel,bout);
  U8:rom
     PORT MAP(address3,sel,cout);
END sin3generator;