controller.vhd

来自「《CPLD_FPGA设计及应用》课件与实例」· VHDL 代码 · 共 29 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY controller IS
  PORT(clk:IN STD_LOGIC;
       datain:IN STD_LOGIC;
       ad:OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
       freq:OUT STD_LOGIC_VECTOR(15 DOWNTO 0));
END controller;
ARCHITECTURE control OF controller IS
  SIGNAL outtemp:STD_LOGIC_VECTOR(16 DOWNTO 0);
BEGIN
  p1:PROCESS(clk,datain)
       VARIABLE temp:STD_LOGIC_VECTOR(16 DOWNTO 0);
     BEGIN
       IF (clk'EVENT AND clk='1') THEN
           temp:=temp(15 DOWNTO 0) & datain;
       END IF;
           outtemp<=temp;
     END PROCESS p1;
  p2:PROCESS(outtemp(16))
     BEGIN
       IF (outtemp(16)='1') THEN
          ad<=outtemp(15 DOWNTO 0);
       ELSE
          freq<=outtemp(15 DOWNTO 0);
       END IF;
     END PROCESS p2;
END control;