iirno.vhd

《CPLD_FPGA设计及应用》课件与实例

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity iirno is 
  port(clk,clr:in std_logic;
       dinxn:in std_logic_vector(9 downto 0);
       regxn0acs,regxn1acs,regxn2acs,dataxnacs:out std_logic_vector(9 downto 0);
       regyn0acs,regyn1acs:out std_logic_vector(9 downto 0);
     --  regxn0bcs,regxn1bcs,regxn2bcs,dataxnbcs:out std_logic_vector(9 downto 0);
     --  regyn0bcs,regyn1bcs:out std_logic_vector(9 downto 0);
       clkregbtcs,clkregcs,clkencs,clrsmcs,nclkencs:out std_logic;
       countercs:out std_logic_vector(3 downto 0);
       counterbtcs:out integer range 9 downto 0;
       resultacs:out std_logic_vector(17 downto 0);
       sumacs:out std_logic_vector(17 downto 0);
    --   resultbcs:out std_logic_vector(17 downto 0);
    --   sumbcs:out std_logic_vector(17 downto 0);
       addxn0acs,addxn1acs,addxn2acs:out std_logic_vector(9 downto 0);
       addyn0acs,addyn1acs:out std_logic_vector(9 downto 0);
    --   addxn0bcs,addxn1bcs,addxn2bcs:out std_logic_vector(9 downto 0);
    --   addyn0bcs,addyn1bcs:out std_logic_vector(9 downto 0);
       datayntempacs:out std_logic_vector(9 downto 0);
   --    datayntempbcs:out std_logic_vector(9 downto 0);
       dataynacs:out std_logic_vector(9 downto 0));
   --    dataynbcs:out std_logic_vector(9 downto 0);
   --    dataynbtemp:out std_logic_vector(9 downto 0));
end iirno;
architecture  iirnox of iirno is
  signal datayna,dataynb:std_logic_vector(9 downto 0);
  signal clkregbt,clkreg,clrsm:std_logic;
  signal clken:std_logic;
  signal counter:std_logic_vector(3 downto 0);
  signal counterbt:integer range 9 downto 0;
  signal resulta:std_logic_vector(17 downto 0);
  signal suma:std_logic_vector(17 downto 0);
  signal addxn0a,addxn1a,addxn2a:std_logic_vector(9 downto 0);
  signal addyn0a,addyn1a:std_logic_vector(9 downto 0);
  signal dataxna,datayntempa,datayntp:std_logic_vector(9 downto 0);
  --signal datayntempa:std_logic_vector(9 downto 0);
  signal regan0a,regan1a,regan2a:std_logic_vector(9 downto 0);
  signal regbn0a,regbn1a:std_logic_vector(9 downto 0);
  signal regxn0a,regxn1a,regxn2a:std_logic_vector(9 downto 0);
  signal regyn0a,regyn1a:std_logic_vector(9 downto 0);

 -- signal resultb:std_logic_vector(17 downto 0);
 -- signal sumb:std_logic_vector(17 downto 0);
 -- signal addxn0b,addxn1b,addxn2b:std_logic_vector(9 downto 0);
 -- signal addyn0b,addyn1b:std_logic_vector(9 downto 0);
 -- signal dataxnb,datayntempb:std_logic_vector(9 downto 0);
 -- signal regan0b,regan1b,regan2b:std_logic_vector(9 downto 0);
 -- signal regbn0b,regbn1b:std_logic_vector(9 downto 0);
 -- signal regxn0b,regxn1b,regxn2b:std_logic_vector(9 downto 0);
 -- signal regyn0b,regyn1b:std_logic_vector(9 downto 0);
begin 
  clkregbt<=not clk and clken;  
  clkregbtcs<=clkregbt;
  clrsm<=not clk and not clken;
  clrsmcs<=clrsm;
 
  p1:process(clk,clr)       --controller
     begin
       if (clr='1')  then
          counter<="0000";
          counterbt<=0;
       elsif(clk'event and clk='1') then
            
           if(counter<10) then
             clken<='1';
   --          clkencs<=clken;
             counter<=counter+1;
     --        counterbt<=counterbt-1;
          else 
             counter<="0000";
             --counterbt<=0;
             clken<='0';
          end if; 
          
          if (counterbt>0) then
             counterbt<=counterbt-1; 
          elsif(counter="1010")  then
             counterbt<=0;
          else
             counterbt<=9;
          end if;
        end if;
         clkencs<=clken;
        countercs<=counter;
        counterbtcs<=counterbt;
     end process p1;
-- clrsm<=counterbt(3) and counterbt(0) and counter(0) and clk
     clkreg<=clk and (not clken);
     clkregcs<=clkreg;
     nclkencs<=not clken;

p2a:process(clkreg,clkregbt,clr,clrsm)  --adder
    begin
       if(clr='1') then
         datayna<=(OTHERS=>'0');
         resulta<=(OTHERS=>'0'); 
       elsif(clkreg='1') then
         datayna<=suma(17 downto 8);    
       elsif(clrsm='1') then
         suma<=(OTHERS=>'0');
         resulta<=(OTHERS=>'0');
         datayntempa<=datayna;
       end if;
      if (clken'event and clken='0') then
          
      if(clkregbt='1') then
        -- suma<=resulta+addxn0a+addxn1a+addxn2a+addyn0a+addyn1a;
          sumax0<=resultaxn0+addxn0a;
          sumax1<=resultaxn1+addxn1a;
          sumax2<=resultaxn2+addxn2a;
          sumay0<=resultayn0+addyn0a;
          sumay1<=resultayn1+addyn1a;
       else
       --    resulta<=suma+suma;
          resultaxn0<=sumax0+sumax0;
          resultaxn1<=sumax1+sumax1;
          resultaxn2<=sumax2+sumax2;
          resultayn0<=sumay0+sumay0;
          resultayn1<=sumay1+sumay1;
       end if;
         addxn0acs<=addxn0a;
         addxn1acs<=addxn1a;
         addxn2acs<=addxn2a;
         resultacs<=resulta;
         sumacs<=suma;
         dataynacs<=datayna;
         datayntempacs<=datayntempa;
     end process p2a;
  p3a:process(clk,clr)  --get the addend
     begin
       if (clrsm='1') then
            addxn0a<="0000000000";
            addxn1a<="0000000000"; 
            addxn2a<="0000000000";
            addyn0a<="0000000000";
            addyn1a<="0000000000";
        elsif (clk'event and clk='0') then
         if (regan0a(counterbt)='1') then
             addxn0a<=regxn0a;
         else 
             addxn0a<="0000000000";
         end if;
         if (regan1a(counterbt)='1') then
             addxn1a<=regxn1a;
         else 
             addxn1a<="0000000000";
         end if;
         if (regan2a(counterbt)='1') then
             addxn2a<=regxn2a;
         else 
             addxn2a<="0000000000";
         end if;
         if (regbn0a(counterbt)='1') then
             addyn0a<=regyn0a;
         else 
             addyn0a<="0000000000";
         end if;
         if (regbn1a(counterbt)='1') then
             addyn1a<=regyn1a;
         else 
             addyn1a<="0000000000";
         end if;
       end if;
     end process p3a;
           regan0a<="0000011100";
           regan1a<="1111100110";
           regan2a<="0000011100";
           regbn0a<="0110010100";
           regbn1a<="1101011011";
 -- p4a:process(clken)  --datain
 --     begin
 --      -- if (clkreg'event and clkreg='0') then
 --       if (clken'event and clken='1') then
 --            dataxna<=dinxn;
 --            datayntp<=datayntempa;
 --       end if;
 --     end process p4a;
 --            dataxnacs<=dataxna;
  p5a:process(clkreg,clr)       --data exchange
     begin
        if (clr='1')  then
             regxn0a<="0000000000";
             regxn1a<="0000000000"; 
             regxn2a<="0000000000";
             regyn0a<="0000000000";
             regyn1a<="0000000000";
       elsif(clken'event and clken='0') then
           regxn2a<=regxn1a;
           regxn1a<=regxn0a;
          -- regxn0a<=dataxna;
           regxn0a<=dinxn;
           regyn1a<=regyn0a;
    --       regyn0a<=datayntp;
    --       regyn0a<=datayntempa;
             regyn0a<=datayna;
       end if;
     end process p5a;
           regxn2acs<=regxn2a;
           regxn1acs<=regxn1a;
           regxn0acs<=regxn0a;
           regyn1acs<=regyn1a;
           regyn0acs<=regyn0a;


--p2b:process(clkreg,clkregbt,clr,clrsm)  --adder
--    begin
--       if(clr='1') then
--         dataynb<=(OTHERS=>'0');
--         resultb<=(OTHERS=>'0'); 
--       elsif(clkreg='1') then
--         dataynb<=suma(17 downto 8); 
--      elsif(clrsm='1') then
--         sumb<=(OTHERS=>'0');
--         resultb<=(OTHERS=>'0');
--      elsif(clkregbt='1') then
--         sumb<=resultb+addxn0b+addxn1b+addxn2b+addyn0b+addyn1b;
--       else
--           resultb<=sumb+sumb;
--       end if;
--   --              datayntempb<=dataynb;
--
--           addxn0bcs<=addxn0b;
--           addxn1bcs<=addxn1b;
--           addxn2bcs<=addxn2b;
--           resultbcs<=resultb;
--           sumbcs<=sumb;
--           dataynbcs<=dataynb;
--           datayntempbcs<=datayntempb;
--     end process p2b;
--  p3b:process(clk,clr)  --get the addend
--     begin
--       if (clrsm='1') then
--            addxn0b<="0000000000";
--            addxn1b<="0000000000"; 
--            addxn2b<="0000000000";
--            addyn0b<="0000000000";
--            addyn1b<="0000000000";
--        elsif (clk'event and clk='0') then
--         if (regan0b(counterbt)='1') then
--             addxn0b<=regxn0b;
--         else 
--             addxn0b<="0000000000";
--         end if;
--         if (regan1b(counterbt)='1') then
--             addxn1b<=regxn1b;
--         else 
--             addxn1b<="0000000000";
--         end if;
--         if (regan2b(counterbt)='1') then
--             addxn2b<=regxn2b;
--         else 
--             addxn2b<="0000000000";
--         end if;
--         if (regbn0b(counterbt)='1') then
--             addyn0b<=regyn0b;
--         else 
--             addyn0b<="0000000000";
--         end if;
--         if (regbn1b(counterbt)='1') then
--             addyn1b<=regyn1b;
--         else 
--             addyn1b<="0000000000";
--         end if;
--       end if;
--     end process p3b;
--           regan0b<="0000111111";
--           regan1b<="1110010011";
--           regan2b<="0000111111";
--           regbn0b<="0111000110";
--           regbn1b<="1100011100";
-- -- p4b:process(clken)  --datain
-- --     begin
-- --      -- if (clkreg'event and clkreg='0') then
-- --       if (clken'event and clken='1') then
-- --            dataxna<=dinxn;
-- --            datayntp<=datayntempa;
-- --       end if;
-- --     end process p4b;
--         --    dataxnbcs<=dataxnb;
--  p5b:process(clkreg,clr)       --data exchange
--     begin
--        if (clr='1')  then
--             regxn0b<="0000000000";
--             regxn1b<="0000000000"; 
--             regxn2b<="0000000000";
--             regyn0b<="0000000000";
--             regyn1b<="0000000000";
--       elsif(clken'event and clken='0') then
--           regxn2b<=regxn1b;
--           regxn1b<=regxn0b;
--           regxn0b<=datayntempa;
--           regyn1b<=regyn0b;
--           regyn0b<=dataynb;
--       end if;
--     end process p5b;
--           regxn2bcs<=regxn2b;
--           regxn1bcs<=regxn1b;
--           regxn0bcs<=regxn0b;
--           regyn1bcs<=regyn1b;
--           regyn0bcs<=regyn0b;
end iirnox;