iirno.map.eqn

《CPLD_FPGA设计及应用》课件与实例

--A1L336 is suma[13]~1138
A1L336 = LCELL(!A1L033 & A1L336 & A1L344 # A1L033 & A1L312);


--A1L136 is suma[12]~1139
A1L136 = LCELL(!A1L033 & A1L136 & A1L344 # A1L033 & A1L902);


--A1L926 is suma[11]~1140
A1L926 = LCELL(!A1L033 & A1L926 & A1L344 # A1L033 & A1L502);


--A1L726 is suma[10]~1141
A1L726 = LCELL(!A1L033 & A1L726 & A1L344 # A1L033 & A1L102);


--A1L526 is suma[9]~1142
A1L526 = LCELL(!A1L033 & A1L526 & A1L344 # A1L033 & A1L791);


--A1L326 is suma[8]~1143
A1L326 = LCELL(!A1L033 & A1L326 & A1L344 # A1L033 & A1L391);


--A1L126 is suma[7]~1144
A1L126 = LCELL(!A1L033 & A1L126 & A1L344 # A1L033 & A1L981);


--A1L916 is suma[6]~1145
A1L916 = LCELL(!A1L033 & A1L916 & A1L344 # A1L033 & A1L581);


--A1L716 is suma[5]~1146
A1L716 = LCELL(!A1L033 & A1L716 & A1L344 # A1L033 & A1L181);


--A1L516 is suma[4]~1147
A1L516 = LCELL(!A1L033 & A1L516 & A1L344 # A1L033 & A1L771);


--A1L316 is suma[3]~1148
A1L316 = LCELL(!A1L033 & A1L316 & A1L344 # A1L033 & A1L371);


--A1L116 is suma[2]~1149
A1L116 = LCELL(!A1L033 & A1L116 & A1L344 # A1L033 & A1L961);


--A1L906 is suma[1]~1150
A1L906 = LCELL(!A1L033 & A1L906 & A1L344 # A1L033 & A1L561);


--A1L706 is suma[0]~1151
A1L706 = LCELL(!A1L033 & A1L706 & A1L344 # A1L033 & A1L161);


--A1L514 is datayntempa[9]~620
A1L514 = LCELL(!A1L344 & A1L483 # A1L344 & A1L514);


--A1L314 is datayntempa[8]~621
A1L314 = LCELL(!A1L344 & A1L283 # A1L344 & A1L314);


--A1L114 is datayntempa[7]~622
A1L114 = LCELL(!A1L344 & A1L083 # A1L344 & A1L114);


--A1L904 is datayntempa[6]~623
A1L904 = LCELL(!A1L344 & A1L873 # A1L344 & A1L904);


--A1L704 is datayntempa[5]~624
A1L704 = LCELL(!A1L344 & A1L673 # A1L344 & A1L704);


--A1L504 is datayntempa[4]~625
A1L504 = LCELL(!A1L344 & A1L473 # A1L344 & A1L504);


--A1L304 is datayntempa[3]~626
A1L304 = LCELL(!A1L344 & A1L273 # A1L344 & A1L304);


--A1L104 is datayntempa[2]~627
A1L104 = LCELL(!A1L344 & A1L073 # A1L344 & A1L104);


--A1L993 is datayntempa[1]~628
A1L993 = LCELL(!A1L344 & A1L863 # A1L344 & A1L993);


--A1L793 is datayntempa[0]~629
A1L793 = LCELL(!A1L344 & A1L663 # A1L344 & A1L793);


--A1L483 is datayna[9]~681
A1L483 = LCELL(!clr & (!clkreg & A1L483 # clkreg & A1L146));


--A1L283 is datayna[8]~682
A1L283 = LCELL(!clr & (!clkreg & A1L283 # clkreg & A1L936));


--A1L083 is datayna[7]~683
A1L083 = LCELL(!clr & (!clkreg & A1L083 # clkreg & A1L736));


--A1L873 is datayna[6]~684
A1L873 = LCELL(!clr & (!clkreg & A1L873 # clkreg & A1L536));


--A1L673 is datayna[5]~685
A1L673 = LCELL(!clr & (!clkreg & A1L673 # clkreg & A1L336));


--A1L473 is datayna[4]~686
A1L473 = LCELL(!clr & (!clkreg & A1L473 # clkreg & A1L136));


--A1L273 is datayna[3]~687
A1L273 = LCELL(!clr & (!clkreg & A1L273 # clkreg & A1L926));


--A1L073 is datayna[2]~688
A1L073 = LCELL(!clr & (!clkreg & A1L073 # clkreg & A1L726));


--A1L863 is datayna[1]~689
A1L863 = LCELL(!clr & (!clkreg & A1L863 # clkreg & A1L526));


--A1L663 is datayna[0]~690
A1L663 = LCELL(!clr & (!clkreg & A1L663 # clkreg & A1L326));


--A1L911 is addyn0a~100
A1L911 = regyn0a[0] & ( !counterbt[1] & !counterbt[0] & (!counterbt[3] $ !counterbt[2]) # counterbt[1] & !counterbt[3] & (!counterbt[2] $ counterbt[0]) );


--A1L021 is addyn0a~101
A1L021 = regyn0a[1] & ( !counterbt[1] & !counterbt[0] & (!counterbt[3] $ !counterbt[2]) # counterbt[1] & !counterbt[3] & (!counterbt[2] $ counterbt[0]) );


--A1L121 is addyn0a~102
A1L121 = regyn0a[2] & ( !counterbt[1] & !counterbt[0] & (!counterbt[3] $ !counterbt[2]) # counterbt[1] & !counterbt[3] & (!counterbt[2] $ counterbt[0]) );


--A1L221 is addyn0a~103
A1L221 = regyn0a[3] & ( !counterbt[1] & !counterbt[0] & (!counterbt[3] $ !counterbt[2]) # counterbt[1] & !counterbt[3] & (!counterbt[2] $ counterbt[0]) );


--A1L321 is addyn0a~104
A1L321 = regyn0a[4] & ( !counterbt[1] & !counterbt[0] & (!counterbt[3] $ !counterbt[2]) # counterbt[1] & !counterbt[3] & (!counterbt[2] $ counterbt[0]) );


--A1L421 is addyn0a~105
A1L421 = regyn0a[5] & ( !counterbt[1] & !counterbt[0] & (!counterbt[3] $ !counterbt[2]) # counterbt[1] & !counterbt[3] & (!counterbt[2] $ counterbt[0]) );


--A1L521 is addyn0a~106
A1L521 = regyn0a[6] & ( !counterbt[1] & !counterbt[0] & (!counterbt[3] $ !counterbt[2]) # counterbt[1] & !counterbt[3] & (!counterbt[2] $ counterbt[0]) );


--A1L621 is addyn0a~107
A1L621 = regyn0a[7] & ( !counterbt[1] & !counterbt[0] & (!counterbt[3] $ !counterbt[2]) # counterbt[1] & !counterbt[3] & (!counterbt[2] $ counterbt[0]) );


--A1L721 is addyn0a~108
A1L721 = regyn0a[8] & ( !counterbt[1] & !counterbt[0] & (!counterbt[3] $ !counterbt[2]) # counterbt[1] & !counterbt[3] & (!counterbt[2] $ counterbt[0]) );


--A1L821 is addyn0a~109
A1L821 = regyn0a[9] & ( !counterbt[1] & !counterbt[0] & (!counterbt[3] $ !counterbt[2]) # counterbt[1] & !counterbt[3] & (!counterbt[2] $ counterbt[0]) );


--clk is clk
--operation mode is input

clk = INPUT();


--dinxn[9] is dinxn[9]
--operation mode is input

dinxn[9] = INPUT();


--clr is clr
--operation mode is input

clr = INPUT();


--dinxn[8] is dinxn[8]
--operation mode is input

dinxn[8] = INPUT();


--dinxn[7] is dinxn[7]
--operation mode is input

dinxn[7] = INPUT();


--dinxn[6] is dinxn[6]
--operation mode is input

dinxn[6] = INPUT();


--dinxn[5] is dinxn[5]
--operation mode is input

dinxn[5] = INPUT();


--dinxn[4] is dinxn[4]
--operation mode is input

dinxn[4] = INPUT();


--dinxn[3] is dinxn[3]
--operation mode is input

dinxn[3] = INPUT();


--dinxn[2] is dinxn[2]
--operation mode is input

dinxn[2] = INPUT();


--dinxn[1] is dinxn[1]
--operation mode is input

dinxn[1] = INPUT();


--dinxn[0] is dinxn[0]
--operation mode is input

dinxn[0] = INPUT();


--regxn0acs[9] is regxn0acs[9]
--operation mode is output

regxn0acs[9] = OUTPUT(regxn0a[9]);


--regxn0acs[8] is regxn0acs[8]
--operation mode is output

regxn0acs[8] = OUTPUT(regxn0a[8]);


--regxn0acs[7] is regxn0acs[7]
--operation mode is output

regxn0acs[7] = OUTPUT(regxn0a[7]);


--regxn0acs[6] is regxn0acs[6]
--operation mode is output

regxn0acs[6] = OUTPUT(regxn0a[6]);


--regxn0acs[5] is regxn0acs[5]
--operation mode is output

regxn0acs[5] = OUTPUT(regxn0a[5]);


--regxn0acs[4] is regxn0acs[4]
--operation mode is output

regxn0acs[4] = OUTPUT(regxn0a[4]);


--regxn0acs[3] is regxn0acs[3]
--operation mode is output

regxn0acs[3] = OUTPUT(regxn0a[3]);


--regxn0acs[2] is regxn0acs[2]
--operation mode is output

regxn0acs[2] = OUTPUT(regxn0a[2]);


--regxn0acs[1] is regxn0acs[1]
--operation mode is output

regxn0acs[1] = OUTPUT(regxn0a[1]);


--regxn0acs[0] is regxn0acs[0]
--operation mode is output

regxn0acs[0] = OUTPUT(regxn0a[0]);


--regxn1acs[9] is regxn1acs[9]
--operation mode is output

regxn1acs[9] = OUTPUT(regxn1a[9]);


--regxn1acs[8] is regxn1acs[8]
--operation mode is output

regxn1acs[8] = OUTPUT(regxn1a[8]);


--regxn1acs[7] is regxn1acs[7]
--operation mode is output

regxn1acs[7] = OUTPUT(regxn1a[7]);


--regxn1acs[6] is regxn1acs[6]
--operation mode is output

regxn1acs[6] = OUTPUT(regxn1a[6]);


--regxn1acs[5] is regxn1acs[5]
--operation mode is output

regxn1acs[5] = OUTPUT(regxn1a[5]);


--regxn1acs[4] is regxn1acs[4]
--operation mode is output

regxn1acs[4] = OUTPUT(regxn1a[4]);


--regxn1acs[3] is regxn1acs[3]
--operation mode is output

regxn1acs[3] = OUTPUT(regxn1a[3]);


--regxn1acs[2] is regxn1acs[2]
--operation mode is output

regxn1acs[2] = OUTPUT(regxn1a[2]);


--regxn1acs[1] is regxn1acs[1]
--operation mode is output

regxn1acs[1] = OUTPUT(regxn1a[1]);


--regxn1acs[0] is regxn1acs[0]
--operation mode is output

regxn1acs[0] = OUTPUT(regxn1a[0]);


--regxn2acs[9] is regxn2acs[9]
--operation mode is output

regxn2acs[9] = OUTPUT(regxn2a[9]);


--regxn2acs[8] is regxn2acs[8]
--operation mode is output

regxn2acs[8] = OUTPUT(regxn2a[8]);


--regxn2acs[7] is regxn2acs[7]
--operation mode is output

regxn2acs[7] = OUTPUT(regxn2a[7]);


--regxn2acs[6] is regxn2acs[6]
--operation mode is output

regxn2acs[6] = OUTPUT(regxn2a[6]);


--regxn2acs[5] is regxn2acs[5]
--operation mode is output

regxn2acs[5] = OUTPUT(regxn2a[5]);


--regxn2acs[4] is regxn2acs[4]
--operation mode is output

regxn2acs[4] = OUTPUT(regxn2a[4]);


--regxn2acs[3] is regxn2acs[3]
--operation mode is output

regxn2acs[3] = OUTPUT(regxn2a[3]);


--regxn2acs[2] is regxn2acs[2]
--operation mode is output

regxn2acs[2] = OUTPUT(regxn2a[2]);


--regxn2acs[1] is regxn2acs[1]
--operation mode is output

regxn2acs[1] = OUTPUT(regxn2a[1]);


--regxn2acs[0] is regxn2acs[0]
--operation mode is output

regxn2acs[0] = OUTPUT(regxn2a[0]);


--dataxnacs[9] is dataxnacs[9]
--operation mode is output

dataxnacs[9] = OUTPUT(GND);


--dataxnacs[8] is dataxnacs[8]
--operation mode is output

dataxnacs[8] = OUTPUT(GND);


--dataxnacs[7] is dataxnacs[7]
--operation mode is output

dataxnacs[7] = OUTPUT(GND);


--dataxnacs[6] is dataxnacs[6]
--operation mode is output

dataxnacs[6] = OUTPUT(GND);


--dataxnacs[5] is dataxnacs[5]
--operation mode is output

dataxnacs[5] = OUTPUT(GND);


--dataxnacs[4] is dataxnacs[4]
--operation mode is output

dataxnacs[4] = OUTPUT(GND);


--dataxnacs[3] is dataxnacs[3]
--operation mode is output

dataxnacs[3] = OUTPUT(GND);


--dataxnacs[2] is dataxnacs[2]
--operation mode is output

dataxnacs[2] = OUTPUT(GND);


--dataxnacs[1] is dataxnacs[1]
--operation mode is output

dataxnacs[1] = OUTPUT(GND);


--dataxnacs[0] is dataxnacs[0]
--operation mode is output

dataxnacs[0] = OUTPUT(GND);


--regyn0acs[9] is regyn0acs[9]
--operation mode is output

regyn0acs[9] = OUTPUT(regyn0a[9]);


--regyn0acs[8] is regyn0acs[8]
--operation mode is output

regyn0acs[8] = OUTPUT(regyn0a[8]);


--regyn0acs[7] is regyn0acs[7]
--operation mode is output

regyn0acs[7] = OUTPUT(regyn0a[7]);


--regyn0acs[6] is regyn0acs[6]
--operation mode is output

regyn0acs[6] = OUTPUT(regyn0a[6]);


--regyn0acs[5] is regyn0acs[5]
--operation mode is output

regyn0acs[5] = OUTPUT(regyn0a[5]);


--regyn0acs[4] is regyn0acs[4]
--operation mode is output

regyn0acs[4] = OUTPUT(regyn0a[4]);


--regyn0acs[3] is regyn0acs[3]
--operation mode is output

regyn0acs[3] = OUTPUT(regyn0a[3]);


--regyn0acs[2] is regyn0acs[2]
--operation mode is output

regyn0acs[2] = OUTPUT(regyn0a[2]);


--regyn0acs[1] is regyn0acs[1]
--operation mode is output

regyn0acs[1] = OUTPUT(regyn0a[1]);


--regyn0acs[0] is regyn0acs[0]
--operation mode is output

regyn0acs[0] = OUTPUT(regyn0a[0]);


--regyn1acs[9] is regyn1acs[9]
--operation mode is output

regyn1acs[9] = OUTPUT(regyn1a[9]);


--regyn1acs[8] is regyn1acs[8]
--operation mode is output

regyn1acs[8] = OUTPUT(regyn1a[8]);


--regyn1acs[7] is regyn1acs[7]
--operation mode is output

regyn1acs[7] = OUTPUT(regyn1a[7]);


--regyn1acs[6] is regyn1acs[6]
--operation mode is output

regyn1acs[6] = OUTPUT(regyn1a[6]);


--regyn1acs[5] is regyn1acs[5]
--operation mode is output

regyn1acs[5] = OUTPUT(regyn1a[5]);


--regyn1acs[4] is regyn1acs[4]
--operation mode is output

regyn1acs[4] = OUTPUT(regyn1a[4]);


--regyn1acs[3] is regyn1acs[3]
--operation mode is output

regyn1acs[3] = OUTPUT(regyn1a[3]);


--regyn1acs[2] is regyn1acs[2]
--operation mode is output

regyn1acs[2] = OUTPUT(regyn1a[2]);


--regyn1acs[1] is regyn1acs[1]
--operation mode is output

regyn1acs[1] = OUTPUT(regyn1a[1]);


--regyn1acs[0] is regyn1acs[0]
--operation mode is output

regyn1acs[0] = OUTPUT(regyn1a[0]);


--clkregbtcs is clkregbtcs
--operation mode is output

clkregbtcs = OUTPUT(A1L033);


--clkregcs is clkregcs
--operation mode is output

clkregcs = OUTPUT(clkreg);


--clkencs is clkencs
--operation mode is output

clkencs = OUTPUT(clken);


--clrsmcs is clrsmcs
--operation mode is output

clrsmcs = OUTPUT(clrsm);


--nclkencs is nclkencs
--operation mode is output

nclkencs = OUTPUT(!clken);


--countercs[3] is countercs[3]
--operation mode is output

countercs[3] = OUTPUT(C1_safe_q[3]);


--countercs[2] is countercs[2]
--operation mode is output

countercs[2] = OUTPUT(C1_safe_q[2]);


--countercs[1] is countercs[1]
--operation mode is output

countercs[1] = OUTPUT(C1_safe_q[1]);


--countercs[0] is countercs[0]
--operation mode is output

countercs[0] = OUTPUT(C1_safe_q[0]);


--counterbtcs[3] is counterbtcs[3]
--operation mode is output