iirno.fit.summary

来自「《CPLD_FPGA设计及应用》课件与实例」· SUMMARY 代码 · 共 15 行

Flow Status : Successful - Thu Apr 20 23:01:35 2006
Quartus II Version : 4.1 Build 181 06/29/2004 SJ Full Version
Revision Name : iirno
Top-level Entity Name : iirno
Family : Stratix II
Total ALUTs : 204 / 12,480 ( 1 % )
Total registers : 109
Total pins : 191 / 343 ( 55 % )
Total memory bits : 0 / 419,328 ( 0 % )
DSP block 9-bit elements : 0 / 96 ( 0 % )
Total PLLs : 0 / 6 ( 0 % )
Total DLLs : 0 / 2 ( 0 % )
Device : EP2S15F484C3
Timing Models : Preliminary