iirno.map.rpt

《CPLD_FPGA设计及应用》课件与实例

; Number of registers using Clock Enable       ; 1     ;
; Number of registers using Output Enable      ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-----------+
; Hierarchy ;
+-----------+
iirno
 |-- lpm_counter:counter_rtl_0
      |-- cntr_m18:auto_generated


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                ;
+---------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+----------------------------------------------------------+
; Compilation Hierarchy Node      ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; Full Hierarchy Name                                      ;
+---------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+----------------------------------------------------------+
; |iirno                          ; 162 (158)         ; 109 (105)    ; 0           ; 0            ; 0       ; 0         ; 0         ; 191  ; 0            ; |iirno                                                   ;
;    |lpm_counter:counter_rtl_0|  ; 4 (0)             ; 4 (0)        ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; |iirno|lpm_counter:counter_rtl_0                         ;
;       |cntr_m18:auto_generated| ; 4 (4)             ; 4 (4)        ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; |iirno|lpm_counter:counter_rtl_0|cntr_m18:auto_generated ;
+---------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+----------------------------------------------------------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in D:/lizi/designiira/iirno.map.eqn.


+--------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                         ;
+--------------------------------------------------------------+-----------------+
; File Name                                                    ; Used in Netlist ;
+--------------------------------------------------------------+-----------------+
; iirno.vhd                                                    ; yes             ;
; d:/altera/quartus41/libraries/megafunctions/lpm_counter.tdf  ; yes             ;
; d:/altera/quartus41/libraries/megafunctions/lpm_constant.inc ; yes             ;
; D:/lizi/designiira/db/cntr_m18.tdf                           ; yes             ;
+--------------------------------------------------------------+-----------------+


+------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary    ;
+----------------------------------------+-------+
; Resource                               ; Usage ;
+----------------------------------------+-------+
; Total combinational functions          ; 162   ;
; ALUT usage by number of inputs         ;       ;
;     -- 7 input functions               ; 0     ;
;     -- 6 input functions               ; 0     ;
;     -- 5 input functions               ; 12    ;
;     -- 4 input functions               ; 79    ;
;     -- <=3 input functions             ; 71    ;
;     -- Combinational cells for routing ; 0     ;
; ALUTs by mode                          ;       ;
;     -- normal mode                     ; 117   ;
;     -- extended LUT mode               ; 0     ;
;     -- arithmetic mode                 ; 15    ;
;     -- shared arithmetic mode          ; 30    ;
; Total registers                        ; 109   ;
; Total ALMs                             ; 84    ;
; I/O pins                               ; 191   ;
; Maximum fan-out node                   ; clr   ;
; Maximum fan-out                        ; 87    ;
; Total fan-out                          ; 1053  ;
; Average fan-out                        ; 2.28  ;
+----------------------------------------+-------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 4.1 Build 181 06/29/2004 SJ Full Version
    Info: Processing started: Thu Apr 20 23:01:05 2006
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off iirno -c iirno
Info: Found 2 design units, including 1 entities, in source file iirno.vhd
    Info: Found design unit 1: iirno-iirnox
    Info: Found entity 1: iirno
Warning: VHDL Process Statement warning at iirno.vhd(87): signal clken is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at iirno.vhd(88): signal counter is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at iirno.vhd(89): signal counterbt is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at iirno.vhd(102): signal suma is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at iirno.vhd(106): signal datayna is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at iirno.vhd(109): signal resulta is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at iirno.vhd(109): signal addxn0a is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at iirno.vhd(109): signal addxn1a is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at iirno.vhd(109): signal addxn2a is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at iirno.vhd(109): signal addyn0a is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at iirno.vhd(109): signal addyn1a is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at iirno.vhd(116): signal suma is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at iirno.vhd(123): signal addxn0a is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at iirno.vhd(124): signal addxn1a is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at iirno.vhd(125): signal addxn2a is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at iirno.vhd(126): signal resulta is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at iirno.vhd(127): signal suma is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at iirno.vhd(128): signal datayna is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at iirno.vhd(129): signal datayntempa is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at iirno.vhd(96): signal or variable datayna may not be assigned a new value in every possible path through the Process Statement. Signal or variable datayna holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: VHDL Process Statement warning at iirno.vhd(96): signal or variable resulta may not be assigned a new value in every possible path through the Process Statement. Signal or variable resulta holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: VHDL Process Statement warning at iirno.vhd(96): signal or variable suma may not be assigned a new value in every possible path through the Process Statement. Signal or variable suma holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: VHDL Process Statement warning at iirno.vhd(96): signal or variable datayntempa may not be assigned a new value in every possible path through the Process Statement. Signal or variable datayntempa holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: VHDL Process Statement warning at iirno.vhd(133): signal clrsm is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at iirno.vhd(189): signal clken is in statement, but is not in sensitivity list
Info: Ignored 55 buffer(s)
    Info: Ignored 55 SOFT buffer(s)
Info: Inferred 1 megafunctions from design logic
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: counter[0]~4
Info: Found 1 design units, including 1 entities, in source file ../../altera/quartus41/libraries/megafunctions/lpm_counter.tdf
    Info: Found entity 1: lpm_counter
Info: Found 1 design units, including 1 entities, in source file db/cntr_m18.tdf
    Info: Found entity 1: cntr_m18
Warning: Output pins are stuck at VCC or GND
    Warning: Pin dataxnacs[9] stuck at GND
    Warning: Pin dataxnacs[8] stuck at GND
    Warning: Pin dataxnacs[7] stuck at GND
    Warning: Pin dataxnacs[6] stuck at GND
    Warning: Pin dataxnacs[5] stuck at GND
    Warning: Pin dataxnacs[4] stuck at GND
    Warning: Pin dataxnacs[3] stuck at GND
    Warning: Pin dataxnacs[2] stuck at GND
    Warning: Pin dataxnacs[1] stuck at GND
    Warning: Pin dataxnacs[0] stuck at GND
    Warning: Pin resultacs[0] stuck at GND
    Warning: Pin addyn0acs[9] stuck at GND
    Warning: Pin addyn0acs[8] stuck at GND
    Warning: Pin addyn0acs[7] stuck at GND
    Warning: Pin addyn0acs[6] stuck at GND
    Warning: Pin addyn0acs[5] stuck at GND
    Warning: Pin addyn0acs[4] stuck at GND
    Warning: Pin addyn0acs[3] stuck at GND
    Warning: Pin addyn0acs[2] stuck at GND
    Warning: Pin addyn0acs[1] stuck at GND
    Warning: Pin addyn0acs[0] stuck at GND
    Warning: Pin addyn1acs[9] stuck at GND
    Warning: Pin addyn1acs[8] stuck at GND
    Warning: Pin addyn1acs[7] stuck at GND
    Warning: Pin addyn1acs[6] stuck at GND
    Warning: Pin addyn1acs[5] stuck at GND
    Warning: Pin addyn1acs[4] stuck at GND
    Warning: Pin addyn1acs[3] stuck at GND
    Warning: Pin addyn1acs[2] stuck at GND
    Warning: Pin addyn1acs[1] stuck at GND
    Warning: Pin addyn1acs[0] stuck at GND
Info: Implemented 403 device resources after synthesis - the final resource count might be different
    Info: Implemented 12 input pins
    Info: Implemented 179 output pins
    Info: Implemented 212 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 57 warnings
    Info: Processing ended: Thu Apr 20 23:01:10 2006
    Info: Elapsed time: 00:00:04