iirno.map.summary

《CPLD_FPGA设计及应用》课件与实例

Flow Status : Successful - Thu Apr 20 23:01:10 2006
Quartus II Version : 4.1 Build 181 06/29/2004 SJ Full Version
Revision Name : iirno
Top-level Entity Name : iirno
Family : Stratix II
Total combinational functions : 162
Total registers : 109
Total pins : 191
Total memory bits : 0
DSP block 9-bit elements : 0
Total PLLs : 0
Total DLLs : 0