my.tim

TMS3205402Verilog HDL源码

                           Performance Summary Report
                           --------------------------

Design:     my
Device:     XC95144XL-10-TQ144
Speed File: Version 3.0
Program:    Timing Report Generator:  version F.28
Date:       Wed Aug 13 01:14:52 2003

Performance Summary:

Pad to Pad (tPD)                          :         11.0ns (1 macrocell levels)
Pad 'RW' to Pad 'D<4>'                                            

Clock net 'IOSTRB' path delays:

Clock Pad to Output Pad (tCO)             :         18.9ns (2 macrocell levels)
Clock Pad 'IOSTRB' to Output Pad 'D<0>'                           (Pterm Clock)

Setup to Clock at the Pad (tSU)           :          2.1ns (0 macrocell levels)
Data signal 'D<4>' to DFF D input Pin at 'EA<19>.D'
Clock pad 'IOSTRB'                                                (Pterm Clock)

                          Minimum Clock Period: 14.0ns
                     Maximum Internal Clock Speed: 71.4Mhz
                         (Limited by Clock Pulse Width)

Clock net 'RW' path delays:

Clock Pad to Output Pad (tCO)             :         18.9ns (2 macrocell levels)
Clock Pad 'RW' to Output Pad 'D<0>'                               (Pterm Clock)

Setup to Clock at the Pad (tSU)           :          2.1ns (0 macrocell levels)
Data signal 'D<4>' to DFF D input Pin at 'EA<19>.D'
Clock pad 'RW'                                                    (Pterm Clock)

                          Minimum Clock Period: 14.0ns
                     Maximum Internal Clock Speed: 71.4Mhz
                         (Limited by Clock Pulse Width)

--------------------------------------------------------------------------------
                            Pad to Pad (tPD) (nsec)

\ From        A     A     A     A     A     A     D     D     D     D     D
 \            1     1     <     <     <     <     <     <     <     <     <
  \           4     5     0     1     2     3     0     1     1     1     1
   \                      >     >     >     >     >     0     1     2     3
    \                                                   >     >     >     >
     \                                                                     
      \                                                                    
       \                                                                   
        \                                                                  
  To     \------------------------------------------------------------------

D<0>       11.0  11.0  11.0  11.0  10.0  10.0                              
D<10>            10.0                                                      
D<11>            10.0                                                      
D<12>            10.0                                                      
D<13>            10.0                                                      
D<14>            10.0                                                      
D<15>            10.0                                                      
D<1>       11.0  11.0  11.0  11.0  10.0  10.0                              
D<2>       10.0  10.0  10.0  10.0  10.0  10.0                              
D<3>       10.0  10.0  10.0  10.0  10.0  10.0                              
D<4>       10.0  10.0  10.0  10.0  10.0  10.0                              
D<5>       10.0  10.0              10.0  10.0                              
D<6>       10.0  10.0              10.0  10.0                              
D<7>       10.0  10.0              10.0  10.0                              
D<8>             10.0                                                      
D<9>             10.0                                                      
DRAM_CE                                                                    
DRAM_RD                                                                    
DRAM_WE                                                                    
FIFOADR0               10.0                                                
FIFOADR1                     10.0                                          
FLASH_CE                                                                   
FLASH_RD                                                                   
FLASH_WE                                                                   
IDE0_CS0   10.0  10.0                                                      
IDE0_CS1   10.0  10.0                                                      
IDE1_CS0   10.0  10.0                                                      
IDE1_CS1   10.0  10.0                                                      
IDE_A<0>               10.0                                                
IDE_A<1>                     10.0                                          
IDE_A<2>                           10.0                                    
IDE_A<3>                                 10.0                              
IDE_D<0>         11.0                           6.5                        
IDE_D<10>        11.0                                10.0                  
IDE_D<11>        11.0                                      10.0            
IDE_D<12>        11.0                                            10.0      
IDE_D<13>        11.0                                                  10.0
IDE_D<14>        11.0                                                      
IDE_D<15>        11.0                                                      
IDE_D<1>         11.0                                                      
IDE_D<2>         11.0                                                      
IDE_D<3>         11.0                                                      
IDE_D<4>         11.0                                                      
IDE_D<5>         11.0                                                      
IDE_D<6>         11.0                                                      
IDE_D<7>         11.0                                                      
IDE_D<8>         11.0                                                      
IDE_D<9>         11.0                                                      
IDE_RD           10.0                                                      
IDE_WR           10.0                                                      
INT3                                                                       
PRAM_CE                                                                    
PRAM_RD                                                                    
PRAM_WE                                                                    
SLCS       10.0  10.0                                                      
SLOE       10.0  10.0                                                      
SLRD       10.0  10.0                                                      
SLWR       10.0  10.0                                                      

--------------------------------------------------------------------------------
                            Pad to Pad (tPD) (nsec)

\ From        D     D     D     D     D     D     D     D     D     D     D
 \            <     <     <     <     <     <     <     <     <     <     <
  \           1     1     1     2     3     4     5     6     7     8     9
   \          4     5     >     >     >     >     >     >     >     >     >
    \         >     >                                                      
     \                                                                     
      \                                                                    
       \                                                                   
        \                                                                  
  To     \------------------------------------------------------------------

D<0>                                                                       
D<10>                                                                      
D<11>                                                                      
D<12>                                                                      
D<13>                                                                      
D<14>                                                                      
D<15>                                                                      
D<1>                                                                       
D<2>                                                                       
D<3>                                                                       
D<4>                                                                       
D<5>                                                                       
D<6>                                                                       
D<7>                                                                       
D<8>                                                                       
D<9>                                                                       
DRAM_CE                                                                    
DRAM_RD                                                                    
DRAM_WE                                                                    
FIFOADR0                                                                   
FIFOADR1                                                                   
FLASH_CE                                                                   
FLASH_RD                                                                   
FLASH_WE                                                                   
IDE0_CS0                                                                   
IDE0_CS1                                                                   
IDE1_CS0                                                                   
IDE1_CS1                                                                   
IDE_A<0>                                                                   
IDE_A<1>                                                                   
IDE_A<2>                                                                   
IDE_A<3>                                                                   
IDE_D<0>                                                                   
IDE_D<10>                                                                  
IDE_D<11>                                                                  
IDE_D<12>                                                                  
IDE_D<13>                                                                  
IDE_D<14>  10.0                                                            
IDE_D<15>        10.0                                                      
IDE_D<1>                6.5                                                
IDE_D<2>                      6.5                                          
IDE_D<3>                            6.5                                    
IDE_D<4>                                  6.5                              
IDE_D<5>                                       10.0                        
IDE_D<6>                                             10.0                  
IDE_D<7>                                                   10.0            
IDE_D<8>                                                         10.0      
IDE_D<9>                                                               10.0
IDE_RD                                                                     
IDE_WR                                                                     
INT3                                                                       
PRAM_CE                                                                    
PRAM_RD                                                                    
PRAM_WE                                                                    
SLCS                                                                       
SLOE                                                                       
SLRD                                                                       
SLWR                                                                       

--------------------------------------------------------------------------------
                            Pad to Pad (tPD) (nsec)