📄 nand_drv.c
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#include "hdcfg.h"
#include "HDRegdef.h"
#include "NAND_DRV.h"
#include "drivermmiif.h"
#include "Driverosif.h"
//#include "mmiSendMessage.h"
//#define _NAND_DEBUG_
//#define _NFLASH_DMA_
//#define _NAND_VERIFY_WRITE_
#define _STAND_ALONE_
#define NAND_POWER_SAVING
#define NAND_SPEED_OPTIMISE
#define GPIO_NUMBER 10
#define NAND_SEL_GPIO_PIN GPIO_NUMBER
#ifndef _NAND_DEBUG_
extern UINT32 MMI_PutString(char *str);
#define DEBUG_OUT(string) MMI_PutString(string)
#else /*_NAND_DEBUG_*/
#define DEBUG_OUT(string) NULL
#endif /*_NAND_DEBUG_*/
#if (NFLASH_TYPE == TYPE_IS_K9F1208X0B)
#define PAGE_PRO_DUMMY_CMD1 0x80
#define PAGE_PRO_DUMMY_CMD2 0x11
#define COPY_BACK_PRO_DUMMY_CMD1 0x00
#define COPY_BACK_PRO_DUMMY_CMD2 0x8a
#define COPY_BACK_PRO_DUMMY_CMD3 0x11
#define READ_MULTI_PLANE_STATUS_CMD 0x71
#endif //(NFLASH_TYPE == TYPE_IS_K9F1208X0B)
/****************Command Sets define start ********************/
#define READ1_CMD_00H 0x00
#define READ1_CMD_01H 0x01
#define READ2_CMD 0x50
#define READ_ID_CMD 0x90
#define RESET_CMD 0xff
#define PAGE_PRO_TRUE_CMD1 0x80
#define PAGE_PRO_TRUE_CMD2 0x10
#define COPY_BACK_PRO_TRUE_CMD1 0x00
#define COPY_BACK_PRO_TRUE_CMD2 0x8a
#define COPY_BACK_PRO_TRUE_CMD3 0x10
#define BLOCK_ERASE_CMD1 0x60
#define BLOCK_ERASE_CMD2 0xd0
#define READ_STATUS_CMD 0x70
/****************Command Sets define end********************/
#if (ASIC_VERSION ==VT3363)
#define mNandWrite_SET_CLE(NaFlash_Cmd) WRITE_REG32((NFLASH_NFCMD_ADDR), (NaFlash_Cmd|0XC0000000))
#elif (ASIC_VERSION==VT3341)
#define mNandWrite_SET_CLE(NaFlash_Cmd) WRITE_REG32((NFLASH_NFCMD_ADDR), (NaFlash_Cmd))
#elif (ASIC_VERSION==VT3360)
#define mNandWrite_SET_CLE(NaFlash_Cmd) WRITE_REG32((NFLASH_NFCMD_ADDR), (NaFlash_Cmd))
#endif
#define mNandWrite_SET_ALE( NaFlash_Adress) WRITE_REG32((NFLASH_NFADDR_ADDR), (NaFlash_Adress))
#define mNand_Read_Data() (READ_REG32((NFLASH_NFDIN_ADDR)))
#define mNand_Write_Data(NFalsh_Data) WRITE_REG32((NFLASH_NFDOUT_ADDR), (NFalsh_Data))
#define SECTOR_SIZE 512
#define NAND_DMA_TIMEOUT_VALUE 100
#define NAND_TIMEOUT_VALUE 0x3FFFF
UINT8 SDAndNandFlag=1 ; /*1: NAND; 0: SD*/
static tNLFASH_INFO_STRUCT gNFlashInfo;
static int NandMountStatus=0;
#ifdef _NAND_VERIFY_WRITE_
UINT8 ReadBackBuf[SECTOR_SIZE];
#endif
#if (DMA_TYPE==TYPE_IS_MOSE_DMA)
extern void ProgramDMAChannel(UINT32 src_addr, UINT32 des_addr, UINT32 ctl);
#endif
#if (DMA_TYPE==TYPE_IS_GPRS_DMA)
extern UINT8 ProgramDMAChannel(UINT32 Source,UINT32 Destination,UINT32 CtlrParam,UINT32 CfgrParam);
#endif
extern UINT16 APIMISC_ObtainDSleepSemaphore (void) ;
extern UINT16 APIMISC_ReleaseDSleepSemaphore (void) ;
extern void EnablePDClk(UINT32 );
extern void DisablePDClk(UINT32 );
//static void NFlashDeselect(void);
//static void NFlashSeselect(void);
void EnableNANDControler(void)
{
UINT32 set_value;
/*enable NFC*/
set_value = READ_REG32(GLOBAL_CGBR1_ADDR) ;/*NFC signal are selected*/
set_value &= 0xf8ffffff;/*disable SD module and NAND*/
set_value = set_value | 0x09000000 ; /*enable NAND module*/
WRITE_REG32(GLOBAL_CGBR1_ADDR,set_value) ;
}
void DisableNANDControler(void)
{
UINT32 temp ;
temp = READ_REG32(GLOBAL_CGBR1_ADDR);
temp &= 0xf0ffffff;/*disable SD module and NAND Pull down Active*/
WRITE_REG32(GLOBAL_CGBR1_ADDR, temp);
}
void EnableNANDClock(void)
{
extern void EnablePDClk( UINT32 ) ;
EnablePDClk(PD_CCKEN_NFC_BIT);
}
void DisableNANDClock(void)
{
extern void DisablePDClk( UINT32 ) ;
DisablePDClk(PD_CCKEN_NFC_BIT);
}
void EnableNANDPower(void)
{
}
void DisableNANDPower(void)
{
}
static void NAND_ObtainSleepSema(void)
{
APIMISC_ObtainDSleepSemaphore();
}
static void NAND_ReleaseSleepSema(void)
{
APIMISC_ReleaseDSleepSemaphore();
}
UINT8 NAND_Mount(void)
{
UINT8 status ;
if(NandMountStatus<0)
return NAND_UNDEFINED_ERR ;
NandMountStatus++ ;
if (NandMountStatus==1)
{ DEBUG_OUT("NAND_Mount\r\n");
EnableNANDPower();
EnableNANDClock();
EnableNANDControler() ;
status=NAND_Init() ;
return status;
}
return NAND_PASS;
}
UINT8 NAND_Unmout(void)
{
NandMountStatus --;
if (NandMountStatus==0)
{
DisableNANDClock();
DisableNANDControler();
DisableNANDPower();
return NAND_PASS;
}
if(NandMountStatus<0)
return NAND_UNDEFINED_ERR ;
return NAND_PASS;
}
/********************************************************************************/
/*****************************Error Correction Code Part Start************************/
/********************************************************************************/
#ifdef NAND_SPEED_OPTIMISE
__inline static void EccClear(void)
#else
static void EccClear(void)
#endif
{
/*clear hardware ecc correction*/
WRITE_REG32(NFLASH_NFECC_ADDR,0x80000000) ;
return ;
}
#ifdef NAND_SPEED_OPTIMISE
__inline static void GenerateEcc(UINT8 *pEccBuf)
#else
static void GenerateEcc(UINT8 *pEccBuf)
#endif
{
UINT32 ecc_code_page ;
/*
*Get the write data Ecc code
* here the ECCECC is not used.
*/
ecc_code_page = READ_REG32(NFLASH_NFECC_ADDR) & 0x3fffffff;
pEccBuf[0] = (UINT8) (ecc_code_page & 0x000000ff);
pEccBuf[1] = (UINT8) ((ecc_code_page >> 8) & 0x000000ff);
pEccBuf[2] = (UINT8) ((ecc_code_page >> 16) & 0x000000ff);
//pEccBuf[3] = (UINT8) ((ecc_code_page >> 24) & 0x0000003f);
return;
}
static NAND_Ret CompareEcc(UINT8 *RdEccBuf, UINT8 *WrEccBuf)
{
if ((RdEccBuf[0] != WrEccBuf[0]) ||
(RdEccBuf[1] != WrEccBuf[1]) ||
(RdEccBuf[2] != WrEccBuf[2]))
{
DEBUG_OUT("Read NAND_ECC_ERR\n\r") ;
return NAND_ECC_ERR ;
}
return NAND_PASS ;
}
/********************************************************************************/
/********************************************************************************/
/********************************************************************************/
/********************************************************************************/
/*****************************Polling Nand FLASh Status Part ************************/
/********************************************************************************/
/*
* Function: ReadStatusRegister( )
* DeSCRiption: This function be used to read the Nand Flash Status register
* Input: None
* Output: None
* Return: return device status
* Others:
*/
static NAND_Ret ReadStatusRegister(void)
{
UINT8 device_status ;
mNandWrite_SET_CLE(READ_STATUS_CMD);
device_status = (UINT8) (mNand_Read_Data() & 0xff) ;
return (device_status) ;
}
/*
* Function: IsSucessProgram( )
* DeSCRiption: This function be used to judge if wirting or erasing is success ,once fail must make the
block invalid
* Input: None
* Output: None
* Return: if success : NAND_PASS ,or lese return NAND_FAIL
* Others:
*/
static NAND_Ret IsSucessProgram(void)
{
UINT8 device_status ;
device_status = ReadStatusRegister();
if ((device_status & TOTAL_PASS_BIT) == 0)
{
return NAND_PASS ;
} /* 1 is sucess*/
return NAND_FAIL ;
}
#ifdef _NAND_DEBUG_
static NAND_Ret IsWriteProtect(void)
{
UINT8 device_status ;
device_status = ReadStatusRegister();
if ((device_status & WRITE_PROTECT_BIT) == WRITE_PROTECT_BIT)
{
return NAND_PASS ;
} /* Not write protect*/
return NAND_FAIL;
}
#endif /*_NAND_DEBUG_*/
/*
* Function: IsReadyToRW( )
* DeSCRiption: This function be used to judge if wirting ,reading or erasing is ready by checking
the Nand controler register
* Input: None
* Output: None
* Return: if success : NAND_PASS ,or lese return NAND_FAIL
* Others:
*/
static NAND_Ret IsReadyToRW(void)
{
UINT32 device_status ;
UINT32 timeout = 1;
device_status = READ_REG32(NFLASH_NFINTP_ADDR) ;
while ((device_status & 0x1) != 0x01)//busy
{
device_status = READ_REG32(NFLASH_NFINTP_ADDR) ;
//timeout++ ;
if ((++timeout) == 0x00fff)
{
WRITE_REG32(NFLASH_NFINTP_ADDR,1) ;
return NAND_FAIL ;
}
}
WRITE_REG32(NFLASH_NFINTP_ADDR,1) ;
return NAND_PASS;
}
static NAND_Ret IsReadyToRW1(void)
{
UINT32 device_status ;
UINT32 EventStatus, EventResult;
extern void HD_EnableInterrupt(UINT32);
EventStatus = OS_DRIVER_WaitEventOR(PERIPH_EVENT_ID,PERIPH_NAND_EVTBIT,&EventResult,
NAND_DMA_TIMEOUT_VALUE);
if (EventStatus == OS_DRIVER_WAIT_EVENT_TIMEOUT)
{
return NAND_FAIL ;
}
else
{
WRITE_REG32(NFLASH_NFINTE_ADDR,0) ;/*Disable NAND INT*/
device_status = READ_REG32(NFLASH_NFINTP_ADDR) ;
WRITE_REG32(NFLASH_NFINTP_ADDR,1) ;
WRITE_REG32(NFLASH_NFINTE_ADDR,1) ;/*Enable NAND INT*/
HD_EnableInterrupt(INT_NAND_BIT);
if ((device_status & 0x1) == 0x01)
{
return NAND_PASS;
}
}
return NAND_FAIL;
}
/********************************************************************************/
/********************************************************************************/
/********************************************************************************/
/********************************************************************************/
/********************************Nand Chip Select and Deselect***********************/
/********************************************************************************/
#ifdef NAND_SPEED_OPTIMISE
__inline static void NFlashSelect(void)
#else
static void NFlashSelect(void)
#endif
{
#if (ASIC_VERSION!=VT3360)
UINT16 gpdir;
UINT16 gpdr;
OS_DRIVER_ObtainSemaphore(GPIO_SEMAPHORE_ID);
/*set the direction of gpio8 as output*/
gpdir = (READ_REG(GPIO_GPDIR_ADDR) & 0xFFFF) | (1 << NAND_SEL_GPIO_PIN); /*GPIO10*/
WRITE_REG(GPIO_GPDIR_ADDR,gpdir);
/*set gpio 8 low to select nand flash chip*/
//gpdr = (READ_REG(GPIO_GPDR_ADDR) & 0XFBFF);/*GPIO10*/
gpdr = (READ_REG(GPIO_GPDR_ADDR) & 0XFFFF) & (~(1 << NAND_SEL_GPIO_PIN));
WRITE_REG(GPIO_GPDR_ADDR,gpdr);
OS_DRIVER_ReleaseSemaphore(GPIO_SEMAPHORE_ID);
#endif/*(ASIC_VERSION!=VT3363)*/
}
#ifdef NAND_SPEED_OPTIMISE
__inline static void NFlashDeselect(void)
#else
static void NFlashDeselect(void)
#endif
{
#if (ASIC_VERSION!=VT3360)
UINT16 gpdir;
UINT16 gpdr;
OS_DRIVER_ObtainSemaphore(GPIO_SEMAPHORE_ID);
/*set the direction of gpio8 as output*/
gpdir = (READ_REG(GPIO_GPDIR_ADDR) & 0xFFFF) | (1 << NAND_SEL_GPIO_PIN);
WRITE_REG(GPIO_GPDIR_ADDR,gpdir);
/*set gpio 8 high to deselect nand flash chip*/
gpdr = (READ_REG(GPIO_GPDR_ADDR) & 0XFFFF) | (1 << NAND_SEL_GPIO_PIN);
WRITE_REG(GPIO_GPDR_ADDR,gpdr);
OS_DRIVER_ReleaseSemaphore(GPIO_SEMAPHORE_ID);
#endif/*(ASIC_VERSION!=VT3363)*/
}
/********************************************************************************/
/********************************************************************************/
/********************************************************************************/
/*
* Function: NFlashDelay( )
* DeSCRiption: This function be used to delay some time make the hardware steady
* Input: UINT32 DelayValue : delay value
* Output: None
* Return: None
* Others:
*/
static void NFlashDelay(UINT32 DelayValue)
{
UINT32 i ;
for (i = 0 ; i < DelayValue+1 ; i++)
NULL ;
return ;
}
/*
* Function: NFlash_Reset( )
* DeSCRiption: This function be used to reset Nand Flash controler
* Input: None
* Output: None
* Return: None
* Others:
*/
void NFlashReset(void)
{
mNandWrite_SET_CLE(RESET_CMD);
NFlashDelay(10) ;
}
/*
* Function: NFlash_ReadID( )
* DeSCRiption: This function be used to read the Nand Flash ID (maker_code,device_code etc)
* Input: None
* Output: None
* Return: return device code
* Others:
*/
static NAND_Ret NFlashReadID(void)
{
/*UINT8 dont_care_code ;*/
#if (NFLASH_TYPE == TYPE_IS_K9F1208X0B)
UINT32 tmp ;
#endif/*#if (NFLASH_TYPE == TYPE_IS_K9F1208X0B) */
mNandWrite_SET_CLE(READ_ID_CMD);
mNandWrite_SET_ALE(0x00) ;
#if (NFLASH_TYPE == TYPE_IS_K9F1208X0B)
gNFlashInfo.maker_code = (UINT8) (mNand_Read_Data() & 0xff) ;
gNFlashInfo.device_code = (UINT8) (mNand_Read_Data() & 0xff) ;
tmp = mNand_Read_Data();
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