vector.s

三星ARM2410boot代码

	AREA VECTOR, CODE, READONLY
;---------------------------------------------------------------------------------------------
	ENTRY
;---------------------------------------------------------------------------------------------
; Note: LDR PC instructions are used here, though branch (B) instructions
; could also be used, unless the ROM is at an address >32MB.
	LDR     PC, =Reset_Handler		;;reset
	nop								;;Undefined
	nop								;;SWI
	nop								;;Prefetch
	nop								;;Abort
	nop								;;Reserved
	LDR     PC, =IRQ_Handler		;;IRQ
	LDR     PC, =FIQ_Handler		;;FIQ

;---------------------------------------------------------------------------------------------
;---------------------------------------------------------------------------------------------
Reset_Handler
	ldr	r1, =P_GPIO_BASE
	ldr	r0, [r1, #P_PORTD_DATA]
	tst  r0,#MODE_TEST
	IMPORT	boot
    beq boot
    tst  r0,#MODE_EMI
    bne boot
    
	mov r0,#0
	mov r1,#0
	mov r2,#0
	mov r3,#0
	mov r4,#0
	mov r6,#0
	mov r7,#0
	mov r8,#0
	mov r9,#0
	mov r10,#0
	mov r11,#0
	mov r12,#0
	mov r13,#0
	mov r14,#0

;	bl	disable_watchdog
	
	;;set stack
	
	;;init stacks
	ldr	r0, =(TCM_RAM_BASE + TCM_RAM_LENGTH)

	msr	CPSR_c, #MODE_FIQ:OR:I_BIT:OR:F_BIT ; No interrupts
	sub	sp, r0, #0

	msr	CPSR_c, #MODE_IRQ:OR:I_BIT:OR:F_BIT ; No interrupts
	sub	sp, r0, #0x80

	msr	CPSR_c, #MODE_SVC:OR:I_BIT:OR:F_BIT ; No interrupts
	sub	sp, r0, #0x100

	mov	r0, #PMC_INT
	bl	en_module_clk

	;;close core intr, and close all intr, open intr mask
	mov	r0, #CORE_INTC_MASK
	bl	en_core_intr
	mvn	r0, #0
	bl	disable_intr
	mvn	r0, #0
	bl	clear_intr_mask
	mov	r0, #PMC_INT
	bl	dis_module_clk

;	ldr r0, =SYS_CLK_48
;	bl	set_pmc_cfg

	IMPORT	main_test
	b	main_test
;---------------------------------------------------------------------------------------------
IRQ_Handler
	sub	r14, r14, #4	;;run next instruction
	stmfd	sp!, {r8-r12, r14}

	ldr	r8, =P_INTR_BASE
	ldr	r9, [r8, #P_INTR_REQ]
	ldr	r10, [r8, #P_INTR_PRIORITY]
	mvn	r10, r10
	ands	r9, r9, r10
	beq	end_IRQ_Handler

end_IRQ_Handler
	ldmfd	sp!, {r8-r12, r15}^	;;return
;---------------------------------------------------------------------------------------------
FIQ_Handler
	sub	r14, r14, #4	;;run next instruction
	stmfd	sp!, {r8-r12, r14}

	ldr	r8, =P_INTR_BASE
	ldr	r9, [r8, #P_INTR_REQ]
	ldr	r10, [r8, #P_INTR_PRIORITY]
	ands	r9, r9, r10
	beq	end_FIQ_Handler

end_FIQ_Handler
	ldmfd	sp!, {r8-r12, r15}^	;;return
;---------------------------------------------------------------------------------------------

;---------------------------------------------------------------------------------------------
;---------------------------------------------------------------------------------------------
      END