pwm.txt

用Verilog语言编写的FPGA控制PWM的程序

module top(clk,rst,code_pulse,pwm_out);

input   clk;//1mhz
input   rst;
output  pwm_out;
input code_pulse;码盘的脉冲

reg [31:0] duty_cycle_r;
reg [31:0] counter;	
reg pwm_out;

parameter clock_divide_r   = 32'd2853;


//PWM利用码盘的脉冲宽度来调整PWM脉冲。每收到5个码盘脉冲，进行依次PWM调整。
reg[3:0] code_count;
always @ (posedge code_pulse or negedge rst)
begin
     if(!rst)code_count<=4'b0000;
     else begin
           code_count<=code_count+1;
          if(code_count==5)
            code_count<=4'b0000;
          end
end

//在每个调整周期内，记录需要的时间。
reg[3:0] code_count_time;
reg[3:0] code_count_time2;
always @ (posedge clk1m or negedge rst)
begin
    if(!rst)begin code_count_time<=4'b0000;code_count_time2<=4'b0000;end
    else begin 
         if(code_count>=0 && code_count<5)
            code_count_time<=code_count_time+1;
         if(code_count==5)
            begin code_count_time2<=code_count_time;
                  code_count_time<=4'b0000;end
         end
end
//PWM调整进程，步径为100个时钟

always @ (posedge clk1m or negedge rst)
begin
    if(!rst) duty_cycle_r<= 32'd2231; 
    if(code_count_time2>=3000)
        begin duty_cycle_r<=duty_cycle_r +32'd100;
              code_count_time2<=4'b0000;end 
end


//计数器进程
always @(posedge clk or negedge rst)         
begin
	if (!rst)begin
		          counter <= 0;
	              end
	else
	begin
		if (counter >= clock_divide_r)
			counter <= 0;
		else 
			counter <= counter + 1;
	end
end
//PWM的控制输出进程
always @(posedge clk or negedge rst)      
begin
	if (!rst)begin
		pwm_out <= 0;
	end
	else 
	begin
		if (counter <= duty_cycle_r)
			pwm_out <= 1'b1;
		else
			pwm_out <= 1'b0;
	end
end


endmodule