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<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html><head> <title></title> <link rel="stylesheet" media="screen" type="text/css" href="./style.css" /> <link rel="stylesheet" media="screen" type="text/css" href="./design.css" /> <link rel="stylesheet" media="print" type="text/css" href="./print.css" /> <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /></head><body><a href=start.html>start</a></br><div class="toc"><div class="tocheader toctoggle" id="toc__header">Table of Contents</div><div id="toc__inside"><ul class="toc"><li class="level1"><div class="li"><span class="li"><a href="#introduction" class="toc">Introduction</a></span></div></li><li class="level1"><div class="li"><span class="li"><a href="#example_interfacing_a_cf_card_in_true_ide_mode" class="toc">Example Interfacing a CF Card in True IDE Mode</a></span></div></li><li class="level1"><div class="li"><span class="li"><a href="#configuring_the_kernel_for_ide_ata_support" class="toc">Configuring the kernel for IDE ATA support</a></span></div><ul class="toc"><li class="level2"><div class="li"><span class="li"><a href="#blackfin_specific_configuration" class="toc">Blackfin specific configuration</a></span></div></li><li class="level2"><div class="li"><span class="li"><a href="#enabling_file_system_support" class="toc">Enabling file system support</a></span></div></li></ul></li><li class="level1"><div class="li"><span class="li"><a href="#testing_the_ide_interface" class="toc">Testing the IDE interface</a></span></div><ul class="toc"><li class="level2"><div class="li"><span class="li"><a href="#kernel_start" class="toc">Kernel Start</a></span></div></li><li class="level2"><div class="li"><span class="li"><a href="#mounting_the_ide_device" class="toc">Mounting the IDE device</a></span></div></li><li class="level2"><div class="li"><span class="li"><a href="#display_drive_content" class="toc">Display drive content</a></span></div></li><li class="level2"><div class="li"><span class="li"><a href="#simple_throughput_test" class="toc">Simple throughput test</a></span></div></li><li class="level2"><div class="li"><span class="li"><a href="#displaying_drive_information" class="toc">Displaying Drive Information</a></span></div></li><li class="level2"><div class="li"><span class="li"><a href="#checking_for_filesystem_support" class="toc">Checking for filesystem support</a></span></div></li><li class="level2"><div class="li"><span class="li"><a href="#checking_disk_space" class="toc">Checking disk space</a></span></div></li><li class="level2"><div class="li"><span class="li"><a href="#validating_data_integrity" class="toc">Validating data integrity</a></span></div></li></ul></li></ul></div></div><h1><a name="introduction" id="introduction">Introduction</a></h1><div class="level1"><p> There is no specific knowledge of the IDE-bus needed to understand how the interface works. Any good search-engine can lead to more than enough sites which provide you with the needed technical info.</p><p><strong>Some Terminology</strong></p><hr /><p><strong>IDE</strong>“”“”<strong>ATA</strong>“”<strong>ATAPI</strong><strong>CFA</strong><strong>DMA</strong><strong>master</strong><strong>PIO</strong><strong>slave</strong><br/> The latest standards define some enhancements, known as the ATA-6 <acronym title="specification">spec</acronym>, which grew out of vendor-specific “Enhanced IDE” (EIDE) implementations.</p><p>The IDE-bus is based on the old MFM-, RLL- and ESDI-harddisks. The idea rose to integrate the controller in the PC with the onboard controller of the harddisk and to attach the result to the harddisk. The only signals needed for the resulting board would be the same signals as those after decoding the complete ISA-bus. These signals together nowadays are the IDE-bus.</p><p>The signals we need for the interface are: </p><ul><li class="level1"><div class="li"> 16 data bits, D0..D15 </div></li><li class="level1"><div class="li"> 3 address lines, A0..A2</div></li><li class="level1"><div class="li"> 2 Register block - select lines, CS0 and CS1 </div></li><li class="level1"><div class="li"> 2 Read/write lines, <acronym title="In other words">IOW</acronym> and IOR</div></li><li class="level1"><div class="li"> 1 Interrupt strobe INTRQ</div></li></ul><p> There is one other strobe but is not needed for the functioning of the interface itself: DASP.</p><p>The function of this line is to blink a LED when the HD is executing a command. There are more lines on the IDE-bus but they are only needed for the extended DMA Modes. The IDE-HD has two blocks of eight registers each: the “Command Block Registers” and the “Control Block Registers”. </p><table class="inline"> <tr> <th> Register </th><th> CS0 </th><th> CS1 </th><th> A2 </th><th> A1 </th><th> A0 </th><th class="rightalign"> Blackfin </th><th> A9 </th><th> A5 </th><th> A4 </th><th> A3 </th><th> A2 </th><th> A1 </th><th class="rightalign"> </th><th> Offset </th><th> AMS0 </th><th> AMS1 </th><th> AMS2 </th><th> AMS3 </th> </tr> <tr> <td class="leftalign"> Data Register(Read and Write) </td><td> 0 </td><td> 1 </td><td> 0 </td><td> 0 </td><td> 0 </td><td class="rightalign"> </td><td> 0 </td><td> 1 </td><td> 0 </td><td> 0 </td><td> 0 </td><td> 0 </td><td class="rightalign"> </td><td> 0×20 </td><td> 0×20000020 </td><td> 0×20100020 </td><td> 0×20200020 </td><td> 0×20300020 </td> </tr> <tr> <td class="leftalign"> Error register (Read) </td><td> 0 </td><td> 1 </td><td> 0 </td><td> 0 </td><td> 1 </td><td class="rightalign"> </td><td> 0 </td><td> 1 </td><td> 0 </td><td> 0 </td><td> 0 </td><td> 1 </td><td class="rightalign"> </td><td> 0×22 </td><td> 0×20000022 </td><td> 0×20100022 </td><td> 0×20200022 </td><td> 0×20300022 </td> </tr> <tr> <td class="leftalign"> Sector count register (Read and Write) </td><td> 0 </td><td> 1 </td><td> 0 </td><td> 1 </td><td> 0 </td><td class="rightalign"> </td><td> 0 </td><td> 1 </td><td> 0 </td><td> 0 </td><td> 1 </td><td> 0 </td><td class="rightalign"> </td><td> 0×24 </td><td> 0×20000024 </td><td> 0×20100024 </td><td> 0×20200024 </td><td> 0×20300024 </td> </tr> <tr> <td class="leftalign"> Sector number register (Read and Write) </td><td> 0 </td><td> 1 </td><td> 0 </td><td> 1 </td><td> 1 </td><td class="rightalign"> </td><td> 0 </td><td> 1 </td><td> 0 </td><td> 0 </td><td> 1 </td><td> 1 </td><td class="rightalign"> </td><td> 0×26 </td><td> 0×20000026 </td><td> 0×20100026 </td><td> 0×20200026 </td><td> 0×20300026 </td> </tr> <tr> <td class="leftalign"> Cylinder Low register (Read and Write) </td><td> 0 </td><td> 1 </td><td> 1 </td><td> 0 </td><td> 0 </td><td class="rightalign"> </td><td> 0 </td><td> 1 </td><td> 0 </td><td> 1 </td><td> 0 </td><td> 0 </td><td class="rightalign"> </td><td> 0×28 </td><td> 0×20000028 </td><td> 0×20100028 </td><td> 0×20200028 </td><td> 0×20300028 </td> </tr> <tr> <td class="leftalign"> Cylinder HIGH register (Read and Write) </td><td> 0 </td><td> 1 </td><td> 1 </td><td> 0 </td><td> 1 </td><td class="rightalign"> </td><td> 0 </td><td> 1 </td><td> 0 </td><td> 1 </td><td> 0 </td><td> 1 </td><td class="rightalign"> </td><td> 0x2A </td><td> 0x2000002A </td><td> 0x2010002A </td><td> 0x2020002A </td><td> 0x2030002A </td> </tr> <tr> <td> Select Card/Head register (Read and Write) </td><td> 0 </td><td> 1 </td><td> 1 </td><td> 1 </td><td> 0 </td><td class="rightalign"> </td><td> 0 </td><td> 1 </td><td> 0 </td><td> 1 </td><td> 1 </td><td> 0 </td><td class="rightalign"> </td><td> 0x2C </td><td> 0x2000002C </td><td> 0x2010002C </td><td> 0x2020002C </td><td> 0x2030002C </td> </tr> <tr> <td class="leftalign"> Status register (Read) </td><td> 0 </td><td> 1 </td><td> 1 </td><td> 1 </td><td> 1 </td><td class="rightalign"> </td><td> 0 </td><td> 1 </td><td> 0 </td><td> 1 </td><td> 1 </td><td> 1 </td><td class="rightalign"> </td><td> 0x2E </td><td> 0x2000002E </td><td> 0x2010002E </td><td> 0x2020002E </td><td> 0x2030002E </td> </tr> <tr> <td class="leftalign"> Alt Status register (Read) </td><td> 1 </td><td> 0 </td><td> 1 </td><td> 1 </td><td> 0 </td><td class="rightalign"> </td><td> 0 </td><td> 0 </td><td> 1 </td><td> 1 </td><td> 1 </td><td> 0 </td><td class="rightalign"> </td><td> 0x1C </td><td> 0x2000001C </td><td> 0x2010001C </td><td> 0x2020001C </td><td> 0x2030001C </td> </tr> <tr> <td class="leftalign"> Feature register (Write) </td><td> 0 </td><td> 1 </td><td> 0 </td><td> 0 </td><td> 1 </td><td class="rightalign"> </td><td> 0 </td><td> 1 </td><td> 0 </td><td> 0 </td><td> 0 </td><td> 1 </td><td class="rightalign"> </td><td> 0×22 </td><td> 0×20000022 </td><td> 0×20100023 </td><td> 0×20200024 </td><td> 0×20300025 </td> </tr> <tr> <td class="leftalign"> Command register (Write) </td><td> 0 </td><td> 1 </td><td> 1 </td><td> 1 </td><td> 1 </td><td class="rightalign"> </td><td> 0 </td><td> 1 </td><td> 0 </td><td> 1 </td><td> 1 </td><td> 1 </td><td class="rightalign"> </td><td> 0x2E </td><td> 0x2000002E </td><td> 0x2010002E </td><td> 0x2020002E </td><td> 0x2030002E </td> </tr> <tr> <td class="leftalign"> Device Control Register (Write) </td><td> 1 </td><td> 0 </td><td> 1 </td><td> 1 </td><td> 0 </td><td class="rightalign"> </td><td> 0 </td><td> 0 </td><td> 1 </td><td> 1 </td><td> 1 </td><td> 0 </td><td class="rightalign"> </td><td> 0x1C </td><td> 0x2000001C </td><td> 0x2010001C </td><td> 0x2020001C </td><td> 0x2030001C </td> </tr></table><br /><p> The first block is chosen by negating CS0, the second by negating CS1.<br/> Applying the right value to the addresslines A0..2 chooses the correct register within each block.<br/> Reading from or writing to a register is done by negating IOR or <acronym title="In other words">IOW</acronym>.<br/> </p><p>The IDE bus is, as said before, 16 bits wide but some of the registers are only 8 bits wide. </p></div><!-- SECTION [1-5048] --><h1><a name="example_interfacing_a_cf_card_in_true_ide_mode" id="example_interfacing_a_cf_card_in_true_ide_mode">Example Interfacing a CF Card in True IDE Mode</a></h1><div class="level1"><p> A CompactFlash Storage Card can be operated in True IDE Mode that is electrically compatible with an<br/> IDE disk drive. The CompactFlash Storage Cards on-card intelligent controller manages interface protocols,<br/> data storage and retrieval as well as Error Correcting Code (ECC), defect handling and diagnostics,<br/> power management and clock control. Once the CompactFlash Storage Card has been configured by the host,<br/> it appears to the host as a standard ATA (IDE) disk drive.<br/></p><p>For further details refer to the CF and ATA-4 specification. </p><table class="inline"> <tr> <th> Blackfin </th><th> </th><th> HDD </th> </tr> <tr> <td> A1 </td><td> → </td><td> A0 </td> </tr> <tr> <td> A2 </td><td> → </td><td> A1 </td> </tr> <tr> <td> A3 </td><td> → </td><td> A2 </td> </tr> <tr> <td> A4 + AMSx </td><td> → </td><td> /CS0 </td> </tr> <tr> <td> A5 + AMSx </td><td> → </td><td> /CS1 </td> </tr> <tr> <td> /ARE </td><td> → </td><td> /IOR </td> </tr> <tr> <td> /AWE </td><td> → </td><td> /<acronym title="In other words">IOW</acronym> </td> </tr> <tr> <td> PFx </td><td> ← </td><td> /INTRQ </td> </tr> <tr> <td> /RESET </td><td> → </td><td class="rightalign"> /RESET </td> </tr> <tr> <td> D[0..15] </td><td> ↔ </td><td> D[0..15] </td> </tr></table><br /><table class="inline"> <tr> <th colspan="3"> For CF Cards in TRUE IDE MODE only </th> </tr> <tr> <td> VCC </td><td class="rightalign"> ← </td><td> /REG </td> </tr> <tr> <td> VCC </td><td class="rightalign"> ← </td><td> /WE </td> </tr> <tr> <td> GND </td><td class="rightalign"> ← </td><td> /ATA_SEL </td> </tr></table><br /><p> <a href="media/cf_ide_interface.png" class="media" target="_blank" title="cf_ide_interface.png"><img src="media/cf_ide_interface.png" class="media" alt="" /></a></p><p> ’</p><p>’ </p><p> A more complex implementation can be found here:</p><p><a href="compactflash_ide_ata_nand_flash_-_interface_card.html" class="wikilink1" title="compactflash_ide_ata_nand_flash_-_interface_card.html">compactflash_ide_ata_nand_flash_-_interface_card</a></p><p><a href="http://blackfin.uclinux.org/frs/?group_id=7" class="urlextern" title="http://blackfin.uclinux.org/frs/?group_id=7" rel="nofollow">http://blackfin.uclinux.org/frs/?group_id=7</a></p></div><!-- SECTION [5049-6345] --><h1><a name="configuring_the_kernel_for_ide_ata_support" id="configuring_the_kernel_for_ide_ata_support">Configuring the kernel for IDE ATA support</a></h1><div class="level1"><p> <a href="media/enable_ide.png" class="media" target="_blank" title="enable_ide.png"><img src="media/enable_ide.png" class="media" alt="" /></a></p><p>Also make sure that:</p><p><strong><*></strong> generic/default IDE chipset support is enabled</p></div><!-- SECTION [6346-6501] --><h2><a name="blackfin_specific_configuration" id="blackfin_specific_configuration">Blackfin specific configuration</a></h2><div class="level2"><ul><li class="level1"><div class="li"> <strong>IDE Extra Configuration</strong></div></li><li class="level1"><div class="li"> <strong>For CF card in TRUE IDE mode</strong><pre class="code"> IDE Interface Address Mapping (see help) (16-bit mapping for multimode CF Interface) ---> (0x2031C020) IDE register base address (0x2031C01C) IDE register alternate address (34) IDE IRQ no (4) IDE IRQ PFx no (13) Blackfin A[x] used as CF A0 (0x20311802) Address for enabling CF TRUE IDE MODE (ATASEL) (0x20311800) Address for disabling CF TRUE IDE MODE (ATASEL) </pre></div></li><li class="level1"><div class="li"> <strong>For IDE Disk</strong></div></li></ul><p><a href="media/enable_ide_extra_config.png" class="media" target="_blank" title="enable_ide_extra_config.png"><img src="media/enable_ide_extra_config.png" class="media" alt="" /></a></p><ul><li class="level1"><div class="li"> <strong>External Bus Interface Unit EBIU Configuration</strong></div></li></ul><p> <a href="media/ebiu_amgctl.png" class="media" target="_blank" title="ebiu_amgctl.png"><img src="media/ebiu_amgctl.png" class="media" alt="" /></a></p><p>⌨️ 快捷键说明
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