📄 using_l1_memory.html
字号:
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html><head> <title></title> <link rel="stylesheet" media="screen" type="text/css" href="./style.css" /> <link rel="stylesheet" media="screen" type="text/css" href="./design.css" /> <link rel="stylesheet" media="print" type="text/css" href="./print.css" /> <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /></head><body><a href=start.html>start</a></br><div class="toc"><div class="tocheader toctoggle" id="toc__header">Table of Contents</div><div id="toc__inside"><ul class="toc"><li class="level1"><div class="li"><span class="li"><a href="#using_l1_memory" class="toc">Using L1 Memory</a></span></div><ul class="toc"><li class="level2"><div class="li"><span class="li"><a href="#placing_pieces_of_kernel_into_l1" class="toc">Placing pieces of kernel into L1</a></span></div></li><li class="level2"><div class="li"><span class="li"><a href="#placing_kernel_modules_into_l1" class="toc">Placing kernel modules into L1</a></span></div></li><li class="level2"><div class="li"><span class="li"><a href="#placing_applications_into_l1" class="toc">Placing Applications into L1</a></span></div><ul class="toc"><li class="level3"><div class="li"><span class="li"><a href="#new_system_calls" class="toc">New system calls</a></span></div></li></ul></li><li class="level2"><div class="li"><span class="li"><a href="#placing_application_stack_into_scratchpad" class="toc">Placing Application Stack into Scratchpad</a></span></div></li></ul></li></ul></div></div><h1><a name="using_l1_memory" id="using_l1_memory">Using L1 Memory</a></h1><div class="level1"><p> Blackfin processors support a hierarchical memory model with different performance and size parameters, depending on the memory location within the hierarchy. Level 1 (L1) memories interconnect closely and efficient with the core for best performance. Separate blocks of L1 memory can be accessed simultaneously through multiple bus systems. Instruction memory is separated from data memory, but unlike classical Harvard architectures, all L1 memory blocks are accessed by one unified addressing scheme. Portions of L1 memory can be configured to function as cache memory. Some Blackfin derivatives also feature on-chip Level 2 (L2) memories. Based on a Von-Neumann architecture, L2 memories have a unified purpose and can freely store instructions and data. Although L2 memories still reside inside the CCLK clock domain, they take multiple CCLK cycles to access. The processors also provide support of an external memory space that includes asynchronous memory space for static RAM devices and synchronous memory space for dynamic RAM such as SDRAM devices. For details on the memory architecture, see the section on <a href="cache_management.html" class="wikilink1" title="cache_management.html">cache management</a>. For memory size, population, and off-chip memory interfaces, refer to the specific Blackfin Processor Hardware Reference manual for your derivative.</p><p>Using the L1 memory blocks are key to being able to effectively and efficient run the Blackfin. Simply turning cache on, will only use 1/2 of the available L1 SRAM in the system, and can run into <a href="http://en.wikipedia.org/wiki/Cache%20pollution" class="interwiki iw_wp" title="http://en.wikipedia.org/wiki/Cache%20pollution">Cache pollution</a> or <a href="http://en.wikipedia.org/wiki/Thrash%20%28computer_science%29" class="interwiki iw_wp" title="http://en.wikipedia.org/wiki/Thrash%20%28computer_science%29">cache thrashing</a>. To prevent these issues, and to best use L1, some experimentation of placing things in L1 (not cached) memory must be done to see how that effects your criteria for overall system performance.</p><p>There are times that a 2x improvement in performance can be made when allocating and managing L1 SDRAM Data banks A and B separately, since loads from both banks can occur simulatiously.</p></div><!-- SECTION [1-1976] --><h2><a name="placing_pieces_of_kernel_into_l1" id="placing_pieces_of_kernel_into_l1">Placing pieces of kernel into L1</a></h2><div class="level2"><p> Parts of the kernel can be placed in L1. This can be done on a function by function basis by using the function <code><em class="u">attribute</em></code> from gcc. Examples of this can be seen in existing <code>C</code> and <code>assembly</code> files. This places code into L1, but data (locals and globals) will still exist on the normal kernel stack in SDRAM:</p></div><!-- SECTION [1977-2523] --><h2><a name="placing_kernel_modules_into_l1" id="placing_kernel_modules_into_l1">Placing kernel modules into L1</a></h2><div class="level2"><p> Here various sections can be used, including:</p><ul><li class="level1"><div class="li"> <code>.data.a.l1</code> - Put data section (initialized data) of kernel module into Data SRAM Bank A</div></li><li class="level1"><div class="li"> <code>.data.b.l1</code> - Put data section (initialized data) of kernel module into Data SRAM Bank B</div></li><li class="level1"><div class="li"> <code>.bss.a.l1</code> - Put bss section (uninitialized data) of kernel module into Data SRAM Bank A</div></li><li class="level1"><div class="li"> <code>.bss.b.l1</code> - Put bss section (uninitialized data) of kernel module into Data SRAM Bank B</div></li><li class="level1"><div class="li"> <code>.text.l1</code> - Put text section (code) of kernel module into Instruction SRAM</div></li></ul><p> This can be done in the source, or at link time. A complete example is shown at how to <a href="load_driver_module_into_l1_memory.html" class="wikilink1" title="load_driver_module_into_l1_memory.html">load driver module into l1 memory</a>.</p></div><!-- SECTION [2524-3208] --><h2><a name="placing_applications_into_l1" id="placing_applications_into_l1">Placing Applications into L1</a></h2><div class="level2"><p>Currently, we can put whole code segment and whole data segment of executable and shared library into L1 SRAM. Putting pecific functions and data into L1 SRAM by gcc attributes has not been implemented.</p><p>Now we have to use FDPIC (elf executables) for this.</p><p>Usage </p><ol><li class="level1"><div class="li"> To put application code into L1 SRAM, adding the following option to gcc when compiling <code>-fno-jump-tables</code> and adding the following options to gcc when linking <code>-pie -Wl,–sep-code -Wl,–code-in-l1 -Wl,-z -Wl,now</code></div></li><li class="level1"><div class="li"> To put shared library code into L1 SRAM, adding the following option to gcc when compiling <code>-fno-jump-tables</code> and adding the following options to gcc when linking <code>-Wl,–sep-code -Wl,–code-in-l1 -Wl,-z -Wl,now</code></div></li><li class="level1"><div class="li"> To put application/shared library data into L1 SRAM, adding the following options to gcc when linking <code>-Wl,–data-in-l1</code></div></li></ol></div><!-- SECTION [3209-4084] --><h3><a name="new_system_calls" id="new_system_calls">New system calls</a></h3><div class="level3"><p> There are now three new Blackfin specific system calls in kernel. They are exported in uClibc. They can be used in both FDPIC and FLAT.</p><p>To use these three functions, you need </p><pre class="code">include <bfin_sram.h>void *sram_alloc (size_t size, unsigned long flags)int sram_free (void *addr)void *dma_memcpy (void *dest, const void *src, size_t size)</pre></div><h4><a name="sram_alloc" id="sram_alloc">sram_alloc</a></h4><div class="level4"><p> <code>void *sram_alloc (size_t size, unsigned long flags)</code> </p><ul><li class="level1"><div class="li"> flags can be anyone or combination of the following values:</div><ol><li class="level2"><div class="li"> L1_INST_SRAM Allocate instruction SRAM</div></li><li class="level2"><div class="li"> L1_DATA_A_SRAM Allocate data A bank SRAM [Currently, it will allocate data B bank SRAM if data A bank cannot be allocated.]</div></li><li class="level2"><div class="li"> L1_DATA_B_SRAM Allocate data B bank SRAM</div></li><li class="level2"><div class="li"> L1_DATA_SRAM Allocate data A or B bank SRAM</div></li></ol></li><li class="level1"><div class="li"> size is the number of the required memory in bytes.</div></li><li class="level1"><div class="li"> return value is the address of the first byte of the allocated memory if success. NULL if fail.</div></li></ul></div><h4><a name="sram_free" id="sram_free">sram_free</a></h4><div class="level4"><p> <code>int sram_free (void *addr)</code> </p><ul><li class="level1"><div class="li"> addr is the first byte of the SRAM memory block. It has to be a value returned by sram_alloc ().</div></li><li class="level1"><div class="li"> return value is 0 if success. -1 if fail.</div></li></ul></div><h4><a name="dma_memcpy" id="dma_memcpy">dma_memcpy</a></h4><div class="level4"><p> <code>void *dma_memcpy (void *dest, const void *src, size_t size)</code></p><p>Like memcpy, except dma_memcpy () copies memory through DMA. So it can be used to copy into or from L1 instruction SRAM.</p><p>The return value is the dest if success. NULL if fail.</p></div><!-- SECTION [4085-5510] --><h2><a name="placing_application_stack_into_scratchpad" id="placing_application_stack_into_scratchpad">Placing Application Stack into Scratchpad</a></h2><div class="level2"></div><!-- SECTION [5511-] --></body></html>⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -