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<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html><head> <title></title> <link rel="stylesheet" media="screen" type="text/css" href="./style.css" /> <link rel="stylesheet" media="screen" type="text/css" href="./design.css" /> <link rel="stylesheet" media="print" type="text/css" href="./print.css" /> <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /></head><body><a href=start.html>start</a></br><div class="toc"><div class="tocheader toctoggle" id="toc__header">Table of Contents</div><div id="toc__inside"><ul class="toc"><li class="clear"><ul class="toc"><li class="level2"><div class="li"><span class="li"><a href="#blackfin_basics" class="toc">Blackfin Basics</a></span></div><ul class="toc"><li class="level3"><div class="li"><span class="li"><a href="#introduction" class="toc">Introduction</a></span></div></li><li class="level3"><div class="li"><span class="li"><a href="#blackfin_peripherals" class="toc">Blackfin Peripherals</a></span></div></li><li class="level3"><div class="li"><span class="li"><a href="#memory_layout" class="toc">Memory Layout</a></span></div></li><li class="level3"><div class="li"><span class="li"><a href="#boot_configurations" class="toc">Boot Configurations</a></span></div></li><li class="level3"><div class="li"><span class="li"><a href="#blackfin.uclinux.org_website" class="toc">blackfin.uclinux.org Website</a></span></div></li></ul></li></ul></li></ul></div></div><h2><a name="blackfin_basics" id="blackfin_basics">Blackfin Basics</a></h2><div class="level2"></div><!-- SECTION [1-27] --><h3><a name="introduction" id="introduction">Introduction</a></h3><div class="level3"><p>Intel and Analog Devices Inc. (ADI) jointly developed the Micro Signal Architecture (MSA) core and introduced it in December of 2000. Since then Intel has put this <a href="http://www.intel.com/design/msa/" class="urlextern" title="http://www.intel.com/design/msa/" rel="nofollow">core</a> in its cell phone chipsets, and ADI has put this core into it’s <a href="http://www.analog.com/blackfin" class="urlextern" title="http://www.analog.com/blackfin" rel="nofollow">Blackfin</a> processor family of devices, which include over 15 different devices/speed grade options , including a dual core chip where each core can run at 600MHz.</p><p>This document will focus on ADI’s ADSP鈥態F533 Blackfin device, which can be found on the BF533 STAMP platform. The MSA core, found in the BF533, has the advantages of a clean, orthogonal, RISC-like microprocessor instruction set. It combines a dual鈥慚AC (Multiply/Accumulate), state鈥憃f鈥憈he鈥慳rt signal processing engine and single-instruction, multiple鈥慸ata (SIMD) multimedia capabilities into a single instruction-set architecture. Since the core was recently developed, it takes advantage of the experience that processor architects have gained over the past 25 years and attempts to meet the needs of DSP, microcontroller, and multimedia processing algorithms that are popular today.</p><p>The DSP features include one instruction port and two separate data ports mapped to a unified 4GB memory space; two 16-bit, single-cycle throughput multipliers; two 40-bit split data ALUs; two 32鈥慴it pointer ALUs with support for circular and bit-reversed addressing; two loop counters that allow nested, zero overhead looping; and hardware support for on-the-fly saturation and clipping. </p><p>The microcontroller features include arbitrary bit manipulation; mixed 16-bit and 32-bit instruction encoding for high code density; memory protection; stack pointers and scratch SRAM for context switching; flexible power management; and an extensible, nested, and prioritized interrupt controller for real-time control.</p><p>The multimedia features include four auxiliary 8-bit data ALUs and a rich set of alignment鈥慽ndependent, packed byte operation instructions. These instructions enable the acceleration of fundamental operations associated with video and imaging based applications.</p></div><!-- SECTION [28-2210] --><h3><a name="blackfin_peripherals" id="blackfin_peripherals">Blackfin Peripherals</a></h3><div class="level3"><p>The Blackfin ADSP鈥態F533 device contains several on-chip peripherals. These include: </p><ul><li class="level1"><div class="li">Parallel Peripheral Interface (PPI)</div></li><li class="level1"><div class="li">Serial Ports (SPORTs)</div></li><li class="level1"><div class="li">Serial Peripheral Interface (SPI)</div></li><li class="level1"><div class="li">General-purpose timers</div></li><li class="level1"><div class="li">Universal Asynchronous Receiver Transmitter (UART)</div></li><li class="level1"><div class="li">Real-Time Clock (RTC)</div></li><li class="level1"><div class="li">Watchdog timer</div></li><li class="level1"><div class="li">General-purpose I/O (programmable flags)</div></li></ul><p>These peripherals are connected to the core via several high bandwidth buses, as shown in Figure 2-1.</p><p> <a href="media/processor_block_diagram.png" class="media" target="_blank" title="processor_block_diagram.png"><img src="media/processor_block_diagram.png" class="media" alt="" /></a></p><p> <em><strong>Figure 2-1. Processor Block Diagram</strong></em></p></div><h4><a name="parallel_peripheral_interface_ppi" id="parallel_peripheral_interface_ppi">Parallel Peripheral Interface (PPI)</a></h4><div class="level4"><p>The processor provides a Parallel Peripheral Interface (PPI) that can connect directly to parallel A/D and D/A converters, ITU-R 601/656 video encoders and decoders, and other general-purpose peripherals. Three distinct ITU-R 656 modes are supported: </p><ul><li class="level1"><div class="li">Active Video Only</div></li><li class="level1"><div class="li">Vertical Blanking Only</div></li><li class="level1"><div class="li">Entire Field</div></li></ul><p>General-purpose modes of the PPI are provided to suit a wide variety of data capture and transmission applications. These modes are divided into four main categories: </p><ul><li class="level1"><div class="li">Data Receive with Internally Generated Frame Syncs</div></li><li class="level1"><div class="li">Data Receive with Externally Generated Frame Syncs</div></li><li class="level1"><div class="li">Data Transmit with Internally Generated Frame Syncs</div></li><li class="level1"><div class="li">Data Transmit with Externally Generated Frame Syncs</div></li></ul></div><h4><a name="serial_ports_sports" id="serial_ports_sports">Serial Ports (SPORTs)</a></h4><div class="level4"><p>The processor incorporates two dual-channel synchronous serial ports (SPORT0 and SPORT1) for serial and multiprocessor communications. The SPORTs support these features: </p><ul><li class="level1"><div class="li"> <strong>I</strong><sup><strong>2</strong></sup><strong>S capable operation</strong></div></li><li class="level1"><div class="li"> <strong>Bidirectional operation</strong> - Each SPORT has two sets of independent transmit and receive pins, enabling eight channels of I<sup>2</sup>S stereo audio.</div></li><li class="level1"><div class="li">Buffered (eight-deep) transmit and receive ports</div></li><li class="level1"><div class="li"> <strong>Clocking</strong> - Each transmit and receive port can either use an external serial clock or generate its own.</div></li><li class="level1"><div class="li"> <strong>Word length</strong> - Each SPORT supports serial data words from 3 to 32 bits in length.</div></li><li class="level1"><div class="li"> <strong>Framing</strong> - Each transmit and receive port can run with or without frame sync signals.</div></li><li class="level1"><div class="li"> <strong>Companding in hardware</strong> - Each SPORT can perform A-law or 碌-law companding according to ITU G.711.</div></li><li class="level1"><div class="li">DMA operations with single-cycle overhead</div></li><li class="level1"><div class="li"> <strong>Interrupts</strong> - Each transmit and receive port can generate an interrupt upon completing the transfer of data.</div></li><li class="level1"><div class="li"> <strong>Multichannel capability</strong> - Each SPORT supports 128 channels out of a 1024-channel window and is compatible with the H.100, H.110, MVIP-90, and HMVIP standards.</div></li></ul></div><h4><a name="serial_peripheral_interface_spi_port" id="serial_peripheral_interface_spi_port">Serial Peripheral Interface (SPI) Port</a></h4><div class="level4"><p>The processor has an SPI-compatible port that enables the processor to communicate with multiple SPI-compatible devices.</p><p>The SPI interface uses three pins for transferring data: two data pins and a clock pin. An SPI chip select input pin lets other SPI devices select the processor, and seven SPI chip select output pins let the processor select other SPI devices. Using these pins, the SPI port provides a full鈥慸uplex, synchronous serial interface, which supports both master and slave modes and multi鈥憁aster environments.</p><p>The SPI port’s baud rate and clock phase/polarities are programmable, and it has an integrated DMA controller, configurable to support either transmit or receive datastreams.</p></div><h4><a name="timers" id="timers">Timers</a></h4><div class="level4"><p>There are four general-purpose programmable timer units in the processor. Three timers have an external pin that can be configured either as a Pulse Width Modulator (PWM) or timer output, as an input to clock the timer, or as a mechanism for measuring pulse widths of external events. </p><p>These timer units can be synchronized to an external clock input connected to the PF1 pin, an external clock input to the PPI_CLK pin, or to the internal SCLK.</p><p>The timers can generate interrupts to the processor core, either to the processor clock or to a count of external signals. In addition to the three general-purpose programmable timers, a fourth timer is also provided. This extra timer is clocked by the internal processor clock and is typically used as a system tick clock for generation of operating system periodic interrupts.</p></div><h4><a name="universal_asynchronous_receiver_transmitter_uart_port" id="universal_asynchronous_receiver_transmitter_uart_port">Universal Asynchronous Receiver Transmitter (UART) Port</a></h4><div class="level4"><p>The processor provides a half-duplex UART port. The UART port supports two modes of operation: </p><ul><li class="level1"><div class="li"> <strong>Programmed I/O</strong> - The processor sends or receives data by writing or reading I/O鈥憁apped UART registers.</div></li><li class="level1"><div class="li"> <strong>Direct Memory Access (DMA)</strong> - The DMA controller transfers both transmit and receive data.</div></li></ul></div><h4><a name="real-time_clock_rtc" id="real-time_clock_rtc">Real-Time Clock (RTC)</a></h4><div class="level4"><p>The processor’s Real-Time Clock (RTC) provides a robust set of digital watch features, including current time, stopwatch, and alarm. The RTC is clocked by a 32.768 kHz crystal external to the processor. The RTC peripheral has dedicated power supply pins, so that it can remain powered up and clocked even when the rest of the processor is in a low power state. The RTC provides several programmable interrupt options. The 32.768 kHz input clock frequency is divided down to a 1 Hz signal by a prescaler. Like the other peripherals, the RTC can wake up the processor from Sleep mode or Deep Sleep mode.</p></div><h4><a name="watchdog_timer" id="watchdog_timer">Watchdog Timer</a></h4><div class="level4"><p>The processor includes a 32-bit timer that can be used to implement a software watchdog function. The programmer initializes the count value of the timer, enables the appropriate interrupt, then enables the timer. Thereafter, the software must reload the counter before it counts to zero from the programmed value.</p></div><h4><a name="programmable_flags" id="programmable_flags">Programmable Flags</a></h4><div class="level4"><p>The processor has 16 bidirectional programmable flag (PF) or general-purpose I/O pins PF[15:0]. Each pin can be individually configured using the flag control, status, and interrupt registers. </p><ul><li class="level1"><div class="li"> <strong>Flag Direction Control register</strong> - Specifies the direction of each individual PFx pin as input or output.</div></li><li class="level1"><div class="li"> <strong>Flag Control and Status registers</strong> -The processor employs a “write-1-to-modify” mechanism that allows any combination of individual flags to be modified in a single instruction, without affecting the level of any other flags.</div></li><li class="level1"><div class="li"> <strong>Flag Interrupt Mask registers</strong> - The two Flag Interrupt Mask registers allow each individual PFx pin to function as an interrupt to the processor. The PFx pins defined as inputs can be configured to generate hardware interrupts, while output PFx pins can be triggered by software interrupts.</div></li><li class="level1"><div class="li"> <strong>Flag Interrupt Sensitivity registers</strong> - The two Flag Interrupt Sensitivity registers specify whether individual PFx pins are level- or edge鈥憇ensitive and specify if edge鈥憇ensitive whether just the rising edge or both the rising and falling edges of the signal are significant.</div></li></ul></div><!-- SECTION [2211-8840] --><h3><a name="memory_layout" id="memory_layout">Memory Layout</a></h3><div class="level3"><p>The Blackfin processor architecture structures memory as a single, unified 4Gbyte address space using 32鈥慴it addresses. All resources, including internal memory, external memory, and I/O control registers, occupy separate sections of this common address space. Level 1 (L1) memories are located on the chip and are faster than the Level 2 (L2) off-chip memories. The memory map of the ADSP-BF533 is given in figure 2鈥⌨️ 快捷键说明
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