riva_hw.c

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(
    RIVA_HW_INST  *chip,
    RIVA_HW_STATE *state
)
{
    /*
     * Save current HW state.
     */
    outb(0x19, 0x3D4); state->repaint0     = inb(0x3D5);
    outb(0x1A, 0x3D4); state->repaint1     = inb(0x3D5);
    outb(0x25, 0x3D4); state->screen       = inb(0x3D5);
    outb(0x28, 0x3D4); state->pixel        = inb(0x3D5);
    outb(0x2D, 0x3D4); state->horiz        = inb(0x3D5);
    outb(0x1B, 0x3D4); state->arbitration0 = inb(0x3D5);
    outb(0x20, 0x3D4); state->arbitration1 = inb(0x3D5);
    outb(0x30, 0x3D4); state->cursor0      = inb(0x3D5);
    outb(0x31, 0x3D4); state->cursor1      = inb(0x3D5);
                      state->cursor2      = chip->PRAMDAC[0x00000300/4];
                      state->vpll         = chip->PRAMDAC[0x00000508/4];
                      state->pllsel       = chip->PRAMDAC[0x0000050C/4];
                      state->general      = chip->PRAMDAC[0x00000600/4];
                      state->config       = chip->PFB[0x00000200/4];
                      switch (chip->Architecture)
                      {
			      case 3:
                              state->offset0  = chip->PGRAPH[0x00000630/4];
                              state->offset1  = chip->PGRAPH[0x00000634/4];
                              state->offset2  = chip->PGRAPH[0x00000638/4];
                              state->offset3  = chip->PGRAPH[0x0000063C/4];
                              state->pitch0   = chip->PGRAPH[0x00000650/4];
                              state->pitch1   = chip->PGRAPH[0x00000654/4];
                              state->pitch2   = chip->PGRAPH[0x00000658/4];
                              state->pitch3   = chip->PGRAPH[0x0000065C/4];
                              break;
			      case 4:
			      case 5:
                              state->offset0  = chip->PGRAPH[0x00000640/4];
                              state->offset1  = chip->PGRAPH[0x00000644/4];
                              state->offset2  = chip->PGRAPH[0x00000648/4];
                              state->offset3  = chip->PGRAPH[0x0000064C/4];
                              state->pitch0   = chip->PGRAPH[0x00000670/4];
                              state->pitch1   = chip->PGRAPH[0x00000674/4];
                              state->pitch2   = chip->PGRAPH[0x00000678/4];
                              state->pitch3   = chip->PGRAPH[0x0000067C/4];
                              break;
                      }
}
static void SetStartAddress
(
    RIVA_HW_INST *chip,
    unsigned      start
)
{
    int offset = start >> 2;
    int pan    = (start & 3) << 1;
    unsigned char tmp;

    /*
     * Unlock extended registers.
     */
    outb(chip->LockUnlockIndex, chip->LockUnlockIO);
    outb(0x57, chip->LockUnlockIO + 1);
    /*
     * Set start address.
     */
    outb(0x0D, 0x3D4);
    outb(offset, 0x3D5);
    outb(0x0C, 0x3D4);
    outb(offset >> 8, 0x3D5);
    outb(0x19, 0x3D4);
    tmp = inb(0x3D5);
    outb(((offset >> 16) & 0x0F) | (tmp & 0xF0), 0x3D5);
    /*
     * 4 pixel pan register.
     */
    offset = inb(chip->IO + 0x0A);
    outb(0x13, 0x3C0);
    outb(pan, 0x3C0);
}
static void nv3SetSurfaces2D
(
    RIVA_HW_INST *chip,
    unsigned     surf0,
    unsigned     surf1
)
{
    while (nv3Busy(chip));
    chip->PGRAPH[0x00000630/4] = surf0;
    chip->PGRAPH[0x00000634/4] = surf1;
}
static void nv4SetSurfaces2D
(
    RIVA_HW_INST *chip,
    unsigned     surf0,
    unsigned     surf1
)
{
    while (nv4Busy(chip));
    chip->PGRAPH[0x00000640/4] = surf0;
    chip->PGRAPH[0x00000644/4] = surf1;
}
static void nv3SetSurfaces3D
(
    RIVA_HW_INST *chip,
    unsigned     surf0,
    unsigned     surf1
)
{
    while (nv3Busy(chip));
    chip->PGRAPH[0x00000638/4] = surf0;
    chip->PGRAPH[0x0000063C/4] = surf1;
}
static void nv4SetSurfaces3D
(
    RIVA_HW_INST *chip,
    unsigned     surf0,
    unsigned     surf1
)
{
    while (nv4Busy(chip));
    chip->PGRAPH[0x00000648/4] = surf0;
    chip->PGRAPH[0x0000064C/4] = surf1;
}

/****************************************************************************\
*                                                                            *
*                      Probe RIVA Chip Configuration                         *
*                                                                            *
\****************************************************************************/

void nv3GetConfig
(
    RIVA_HW_INST *chip
)
{
    /*
     * Fill in chip configuration.
     */
    if (chip->PFB[0x00000000/4] & 0x00000020)
    {
        if (((chip->PMC[0x00000000/4] & 0xF0) == 0x20)
         && ((chip->PMC[0x00000000/4] & 0x0F) >= 0x02))
        {        
            /*
             * SDRAM 128 ZX.
             */
            chip->RamBandwidthKBytesPerSec = 800000;
            switch (chip->PFB[0x00000000/4] & 0x03)
            {
                case 2:
                    chip->RamAmountKBytes = 1024 * 4 - 32;
                    break;
                case 1:
                    chip->RamAmountKBytes = 1024 * 2 - 32;
                    break;
                default:
                    chip->RamAmountKBytes = 1024 * 8 - 32;
                    break;
            }
        }            
        else            
        {
            chip->RamBandwidthKBytesPerSec = 1000000;
            chip->RamAmountKBytes          = 1024 * 8 - 32;
        }            
    }
    else
    {
        /*
         * SGRAM 128.
         */
        chip->RamBandwidthKBytesPerSec = 1000000;
        switch (chip->PFB[0x00000000/4] & 0x00000003)
        {
            case 0:
                chip->RamAmountKBytes = 1024 * 8 - 32;
                break;
            case 2:
                chip->RamAmountKBytes = 1024 * 4 - 32;
                break;
            default:
                chip->RamAmountKBytes = 1024 * 2 - 32;
                break;
        }
    }        
    chip->CrystalFreqKHz   = (chip->PEXTDEV[0x00000000/4] & 0x00000020) ? 14318 : 13500;
    chip->CURSOR           = &(chip->PRAMIN[0x00008000/4 - 0x0800/4]);
    chip->CURSORPOS        = &(chip->PRAMDAC[0x0300/4]);
    chip->VBLANKENABLE     = &(chip->PGRAPH[0x0140/4]);
    chip->VBLANK           = &(chip->PGRAPH[0x0100/4]);
    chip->VBlankBit        = 0x00000100;
    chip->MaxVClockFreqKHz = 230000;
    chip->LockUnlockIO     = 0x3C4;
    chip->LockUnlockIndex  = 0x06;
    /*
     * Set chip functions.
     */
    chip->Busy            = nv3Busy;
    chip->ShowHideCursor  = ShowHideCursor;
    chip->CalcStateExt    = CalcStateExt;
    chip->LoadStateExt    = LoadStateExt;
    chip->UnloadStateExt  = UnloadStateExt;
    chip->SetStartAddress = SetStartAddress;
    chip->SetSurfaces2D   = nv3SetSurfaces2D;
    chip->SetSurfaces3D   = nv3SetSurfaces3D;
}

void nv4GetConfig
(
    RIVA_HW_INST *chip
)
{
    /*
     * Fill in chip configuration.
     */
    switch (chip->PFB[0x00000000/4] & 0x00000003)
    {
        case 0:
            chip->RamAmountKBytes = 1024 * 32 - 128;
            break;
        case 1:
            chip->RamAmountKBytes = 1024 * 4 - 128;
            break;
        case 2:
            chip->RamAmountKBytes = 1024 * 8 - 128;
            break;
        case 3:
        default:
            chip->RamAmountKBytes = 1024 * 16 - 128;
            break;
    }
    switch ((chip->PFB[0x00000000/4] >> 3) & 0x00000003)
    {
        case 3:
            chip->RamBandwidthKBytesPerSec = 800000;
            break;
        default:
            chip->RamBandwidthKBytesPerSec = 1000000;
            break;
    }
    chip->CrystalFreqKHz   = (chip->PEXTDEV[0x00000000/4] & 0x00000040) ? 14318 : 13500;
    chip->CURSOR           = &(chip->PRAMIN[0x00010000/4 - 0x0800/4]);
    chip->CURSORPOS        = &(chip->PRAMDAC[0x0300/4]);
    chip->VBLANKENABLE     = &(chip->PCRTC[0x0140/4]);
    chip->VBLANK           = &(chip->PCRTC[0x0100/4]);
    chip->VBlankBit        = 0x00000001;
    chip->MaxVClockFreqKHz = 250000;
    chip->LockUnlockIO     = 0x3D4;
    chip->LockUnlockIndex  = 0x1F;
    /*
     * Set chip functions.
     */
    chip->Busy            = nv4Busy;
    chip->ShowHideCursor  = ShowHideCursor;
    chip->CalcStateExt    = CalcStateExt;
    chip->LoadStateExt    = LoadStateExt;
    chip->UnloadStateExt  = UnloadStateExt;
    chip->SetStartAddress = SetStartAddress;
    chip->SetSurfaces2D   = nv4SetSurfaces2D;
    chip->SetSurfaces3D   = nv4SetSurfaces3D;
}

void nv5GetConfig
(
    RIVA_HW_INST *chip
)
{
    /*
     * Fill in chip configuration.
     */
    switch (chip->PFB[0x00000000/4] & 0x00000003)
    {
        case 0:
            chip->RamAmountKBytes = 1024 * 32 - 128;
            break;
        case 1:
            chip->RamAmountKBytes = 1024 * 4 - 128;
            break;
        case 2:
            chip->RamAmountKBytes = 1024 * 8 - 128;
            break;
        case 3:
        default:
            chip->RamAmountKBytes = 1024 * 16 - 128;
            break;
    }
    switch ((chip->PFB[0x00000000/4] >> 3) & 0x00000003)
    {
        case 3:
            chip->RamBandwidthKBytesPerSec = 800000;
            break;
        default:
            chip->RamBandwidthKBytesPerSec = 1000000;
            break;
    }
    chip->CrystalFreqKHz   = (chip->PEXTDEV[0x00000000/4] & 0x00000040) ? 14318 : 13500;
    chip->CURSOR           = &(chip->PRAMIN[0x00010000/4 - 0x0800/4]);
    chip->CURSORPOS        = &(chip->PRAMDAC[0x0300/4]);
    chip->VBLANKENABLE     = &(chip->PCRTC[0x0140/4]);
    chip->VBLANK           = &(chip->PCRTC[0x0100/4]);
    chip->VBlankBit        = 0x00000001;
    chip->MaxVClockFreqKHz = 250000;
    chip->LockUnlockIO     = 0x3D4;
    chip->LockUnlockIndex  = 0x1F;
    /*
     * Set chip functions.
     */
    chip->Busy            = nv4Busy;
    chip->ShowHideCursor  = ShowHideCursor;
    chip->CalcStateExt    = CalcStateExt;
    chip->LoadStateExt    = LoadStateExt;
    chip->UnloadStateExt  = UnloadStateExt;
    chip->SetStartAddress = SetStartAddress;
    chip->SetSurfaces2D   = nv4SetSurfaces2D;
    chip->SetSurfaces3D   = nv4SetSurfaces3D;
}

int RivaGetConfig
(
    RIVA_HW_INST *chip
)
{
    /*
     * Save this so future SW know whats it's dealing with.
     */
    chip->Version = RIVA_SW_VERSION;
    /*
     * Chip specific configuration.
     */
    switch (chip->Architecture)
    {
        case 3:
            nv3GetConfig(chip);
            break;
        case 4:
            nv4GetConfig(chip);
            break;
	    case 5:
	    nv5GetConfig(chip);
        default:
            return (-1);
    }
    /*
     * Fill in FIFO pointers.
     */
    chip->Rop    = (RivaRop                 *)&(chip->FIFO[0x00000000/4]);
    chip->Clip   = (RivaClip                *)&(chip->FIFO[0x00002000/4]);
    chip->Patt   = (RivaPattern             *)&(chip->FIFO[0x00004000/4]);
    chip->Pixmap = (RivaPixmap              *)&(chip->FIFO[0x00006000/4]);
    chip->Blt    = (RivaScreenBlt           *)&(chip->FIFO[0x00008000/4]);
    chip->Bitmap = (RivaBitmap              *)&(chip->FIFO[0x0000A000/4]);
    chip->Tri03  = (RivaTexturedTriangle03  *)&(chip->FIFO[0x0000E000/4]);
    return (0);
}