riva_hw.c

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                if (mclk_extra ==0)   found = 1;
                mclk_extra--;
            }
        }
        craw = clwm;
        vraw = vlwm;
        if (clwm < 384) clwm = 384;
        if (vlwm < 128) vlwm = 128;
        data = (int)(clwm);
        fifo->graphics_lwm = data;
        fifo->graphics_burst_size = 128;
        data = (int)((vlwm+15));
        fifo->video_lwm = data;
        fifo->video_burst_size = vbs;
    }
}
static void nv4UpdateArbitrationSettings
(
    unsigned      VClk, 
    unsigned      pixelDepth, 
    unsigned     *burst,
    unsigned     *lwm,
    RIVA_HW_INST *chip
)
{
    nv4_fifo_info fifo_data;
    nv4_sim_state sim_data;
    unsigned int M, N, P, pll, MClk, NVClk, cfg1;

    pll = chip->PRAMDAC[0x00000504/4];
    M = (pll >> 0)  & 0xFF; N = (pll >> 8)  & 0xFF; P = (pll >> 16) & 0x0F;
    MClk  = (N * chip->CrystalFreqKHz / M) >> P;
    pll = chip->PRAMDAC[0x00000500/4];
    M = (pll >> 0)  & 0xFF; N = (pll >> 8)  & 0xFF; P = (pll >> 16) & 0x0F;
    NVClk  = (N * chip->CrystalFreqKHz / M) >> P;
    cfg1 = chip->PFB[0x00000204/4];
    sim_data.pix_bpp        = (char)pixelDepth;
    sim_data.enable_video   = 0;
    sim_data.enable_mp      = 0;
    sim_data.memory_width   = (chip->PEXTDEV[0x00000000/4] & 0x10) ? 128 : 64;
    sim_data.mem_latency    = (char)cfg1 & 0x0F;
    sim_data.mem_aligned    = 1;
    sim_data.mem_page_miss  = (char)(((cfg1 >> 4) &0x0F) + ((cfg1 >> 31) & 0x01));
    sim_data.gr_during_vid  = 0;
    sim_data.pclk_khz       = VClk;
    sim_data.mclk_khz       = MClk;
    sim_data.nvclk_khz      = NVClk;
    nv4CalcArbitration(&fifo_data, &sim_data);
    if (fifo_data.valid)
    {
        int  b = fifo_data.graphics_burst_size >> 4;
        *burst = 0;
        while (b >>= 1) (*burst)++;
        *lwm   = fifo_data.graphics_lwm >> 3;
    }
}

/****************************************************************************\
*                                                                            *
*                          RIVA Mode State Routines                          *
*                                                                            *
\****************************************************************************/

/*
 * Calculate the Video Clock parameters for the PLL.
 */
static int CalcVClock
(
    int           clockIn,
    int          *clockOut,
    int          *mOut,
    int          *nOut,
    int          *pOut,
    RIVA_HW_INST *chip
)
{
    unsigned lowM, highM, highP;
    unsigned DeltaNew, DeltaOld;
    unsigned VClk, Freq;
    unsigned M, N, P;
    
    DeltaOld = 0xFFFFFFFF;
    VClk     = (unsigned)clockIn;
    if (chip->CrystalFreqKHz == 14318)
    {
        lowM  = 8;
        highM = 14 - (chip->Architecture == 3);
    }
    else
    {
        lowM  = 7;
        highM = 13 - (chip->Architecture == 3);
    }                      
    highP = 4 - (chip->Architecture == 3);
    for (P = 0; P <= highP; P ++)
    {
        Freq = VClk << P;
        if ((Freq >= 128000) && (Freq <= chip->MaxVClockFreqKHz))
        {
            for (M = lowM; M <= highM; M++)
            {
                N    = (VClk * M / chip->CrystalFreqKHz) << P;
                Freq = (chip->CrystalFreqKHz * N / M) >> P;
                if (Freq > VClk)
                    DeltaNew = Freq - VClk;
                else
                    DeltaNew = VClk - Freq;
                if (DeltaNew < DeltaOld)
                {
                    *mOut     = M;
                    *nOut     = N;
                    *pOut     = P;
                    *clockOut = Freq;
                    DeltaOld  = DeltaNew;
                }
            }
        }
    }
    return (DeltaOld != 0xFFFFFFFF);
}
/*
 * Calculate extended mode parameters (SVGA) and save in a 
 * mode state structure.
 */
static void CalcStateExt
(
    RIVA_HW_INST  *chip,
    RIVA_HW_STATE *state,
    int            bpp,
    int            width,
    int            hDisplaySize,
    int            hDisplay,
    int            hStart,
    int            hEnd,
    int            hTotal,
    int            height,
    int            vDisplay,
    int            vStart,
    int            vEnd,
    int            vTotal,
    int            dotClock
)
{
    int pixelDepth, VClk, m, n, p;
    /*
     * Save mode parameters.
     */
    state->bpp    = bpp;
    state->width  = width;
    state->height = height;
    /*
     * Extended RIVA registers.
     */
    pixelDepth = (bpp + 1)/8;
    CalcVClock(dotClock, &VClk, &m, &n, &p, chip);
    switch (chip->Architecture)
    {
	    case 3:
            nv3UpdateArbitrationSettings(VClk, 
                                         pixelDepth * 8, 
                                        &(state->arbitration0),
                                        &(state->arbitration1),
                                         chip);
            state->cursor0  = 0x00;
            state->cursor1  = 0x78;
            state->cursor2  = 0x00000000;
            state->pllsel   = 0x10010100;
            state->config   = ((width + 31)/32)
                            | (((pixelDepth > 2) ? 3 : pixelDepth) << 8)
                            | 0x1000;
            state->general  = 0x00000100;
            state->repaint1 = hDisplaySize < 1280 ? 0x06 : 0x02;
            break;
	    case 4:
	    case 5:
            nv4UpdateArbitrationSettings(VClk, 
                                         pixelDepth * 8, 
                                        &(state->arbitration0),
                                        &(state->arbitration1),
                                         chip);
            state->cursor0  = 0x00;
            state->cursor1  = 0xFC;
            state->cursor2  = 0x00000000;
            state->pllsel   = 0x10000700;
            state->config   = 0x00001114;
            state->general  = bpp == 16 ? 0x00101100 : 0x00100100;
            state->repaint1 = hDisplaySize < 1280 ? 0x04 : 0x00;
            break;
    }
    state->vpll     = (p << 16) | (n << 8) | m;
    state->screen   = ((hTotal   & 0x040) >> 2)
                    | ((vDisplay & 0x400) >> 7)
                    | ((vStart   & 0x400) >> 8)
                    | ((vDisplay & 0x400) >> 9)
                    | ((vTotal   & 0x400) >> 10);
    state->repaint0 = (((width/8)*pixelDepth) & 0x700) >> 3;
    state->horiz    = hTotal     < 260 ? 0x00 : 0x01;
    state->pixel    = (pixelDepth > 2 ? 3 : pixelDepth) | 0x40;
    state->offset0  =
    state->offset1  =
    state->offset2  =
    state->offset3  = 0;
    state->pitch0   =
    state->pitch1   =
    state->pitch2   =
    state->pitch3   = pixelDepth * width;
}
/*
 * Load fixed function state and pre-calculated/stored state.
 */
#define LOAD_FIXED_STATE(tbl,dev)                                       \
    for (i = 0; i < sizeof(tbl##Table##dev)/8; i++)                 \
        chip->dev[tbl##Table##dev[i][0]] = tbl##Table##dev[i][1]
#define LOAD_FIXED_STATE_8BPP(tbl,dev)                                  \
    for (i = 0; i < sizeof(tbl##Table##dev##_8BPP)/8; i++)            \
        chip->dev[tbl##Table##dev##_8BPP[i][0]] = tbl##Table##dev##_8BPP[i][1]
#define LOAD_FIXED_STATE_15BPP(tbl,dev)                                 \
    for (i = 0; i < sizeof(tbl##Table##dev##_15BPP)/8; i++)           \
        chip->dev[tbl##Table##dev##_15BPP[i][0]] = tbl##Table##dev##_15BPP[i][1]
#define LOAD_FIXED_STATE_16BPP(tbl,dev)                                 \
    for (i = 0; i < sizeof(tbl##Table##dev##_16BPP)/8; i++)           \
        chip->dev[tbl##Table##dev##_16BPP[i][0]] = tbl##Table##dev##_16BPP[i][1]
#define LOAD_FIXED_STATE_32BPP(tbl,dev)                                 \
    for (i = 0; i < sizeof(tbl##Table##dev##_32BPP)/8; i++)           \
        chip->dev[tbl##Table##dev##_32BPP[i][0]] = tbl##Table##dev##_32BPP[i][1]
static void LoadStateExt
(
    RIVA_HW_INST  *chip,
    RIVA_HW_STATE *state
)
{
    int i;
    /*
     * Load HW fixed function state.
     */
    LOAD_FIXED_STATE(Riva,PMC);
    LOAD_FIXED_STATE(Riva,PTIMER);
    /*
     * Make sure frame buffer config gets set before loading PRAMIN.
     */
    chip->PFB[0x00000200/4] = state->config;
    switch (chip->Architecture)
    {
        case 3:
            LOAD_FIXED_STATE(nv3,PFIFO);
            LOAD_FIXED_STATE(nv3,PRAMIN);
            LOAD_FIXED_STATE(nv3,PGRAPH);
            switch (state->bpp)
            {
                case 15:
                case 16:
                    LOAD_FIXED_STATE_15BPP(nv3,PRAMIN);
                    LOAD_FIXED_STATE_15BPP(nv3,PGRAPH);
                    chip->Tri03 = (RivaTexturedTriangle03  *)&(chip->FIFO[0x0000E000/4]);
                    break;
                case 24:
                case 32:
                    LOAD_FIXED_STATE_32BPP(nv3,PRAMIN);
                    LOAD_FIXED_STATE_32BPP(nv3,PGRAPH);
                    chip->Tri03 = 0L;
                    break;
                case 8:
                default:
                    LOAD_FIXED_STATE_8BPP(nv3,PRAMIN);
                    LOAD_FIXED_STATE_8BPP(nv3,PGRAPH);
                    chip->Tri03 = 0L;
                    break;
            }
            for (i = 0x00000; i < 0x00800; i++)
                chip->PRAMIN[0x00000502 + i] = (i << 12) | 0x03;
            chip->PGRAPH[0x00000630/4] = state->offset0;
            chip->PGRAPH[0x00000634/4] = state->offset1;
            chip->PGRAPH[0x00000638/4] = state->offset2;
            chip->PGRAPH[0x0000063C/4] = state->offset3;
            chip->PGRAPH[0x00000650/4] = state->pitch0;
            chip->PGRAPH[0x00000654/4] = state->pitch1;
            chip->PGRAPH[0x00000658/4] = state->pitch2;
            chip->PGRAPH[0x0000065C/4] = state->pitch3;
            break;
	    case 4:
	    case 5:
            LOAD_FIXED_STATE(nv4,PFIFO);
            LOAD_FIXED_STATE(nv4,PRAMIN);
            LOAD_FIXED_STATE(nv4,PGRAPH);
            switch (state->bpp)
            {
                case 15:
                    LOAD_FIXED_STATE_15BPP(nv4,PRAMIN);
                    LOAD_FIXED_STATE_15BPP(nv4,PGRAPH);
                    chip->Tri03 = (RivaTexturedTriangle03  *)&(chip->FIFO[0x0000E000/4]);
                    break;
                case 16:
                    LOAD_FIXED_STATE_16BPP(nv4,PRAMIN);
                    LOAD_FIXED_STATE_16BPP(nv4,PGRAPH);
                    chip->Tri03 = (RivaTexturedTriangle03  *)&(chip->FIFO[0x0000E000/4]);
                    break;
                case 24:
                case 32:
                    LOAD_FIXED_STATE_32BPP(nv4,PRAMIN);
                    LOAD_FIXED_STATE_32BPP(nv4,PGRAPH);
                    chip->Tri03 = 0L;
                    break;
                case 8:
                default:
                    LOAD_FIXED_STATE_8BPP(nv4,PRAMIN);
                    LOAD_FIXED_STATE_8BPP(nv4,PGRAPH);
                    chip->Tri03 = 0L;
                    break;
            }
            chip->PGRAPH[0x00000640/4] = state->offset0;
            chip->PGRAPH[0x00000644/4] = state->offset1;
            chip->PGRAPH[0x00000648/4] = state->offset2;
            chip->PGRAPH[0x0000064C/4] = state->offset3;
            chip->PGRAPH[0x00000670/4] = state->pitch0;
            chip->PGRAPH[0x00000674/4] = state->pitch1;
            chip->PGRAPH[0x00000678/4] = state->pitch2;
            chip->PGRAPH[0x0000067C/4] = state->pitch3;
            break;
    }
//NOTICE("8");
//    LOAD_FIXED_STATE(Riva,FIFO); /* FIX ME*/
//NOTICE("9");
    /*
     * Load HW mode state.
     */
    outb(0x19, 0x3D4); outb(state->repaint0, 0x3D5);
    outb(0x1A, 0x3D4); outb(state->repaint1, 0x3D5);
    outb(0x25, 0x3D4); outb(state->screen, 0x3D5);
    outb(0x28, 0x3D4); outb(state->pixel, 0x3D5);
    outb(0x2D, 0x3D4); outb(state->horiz, 0x3D5);
    outb(0x1B, 0x3D4); outb(state->arbitration0, 0x3D5);
    outb(0x20, 0x3D4); outb(state->arbitration1, 0x3D5);
    outb(0x30, 0x3D4); outb(state->cursor0, 0x3D5);
    outb(0x31, 0x3D4); outb(state->cursor1, 0x3D5);
    chip->PRAMDAC[0x00000300/4]  = state->cursor2;
    chip->PRAMDAC[0x00000508/4]  = state->vpll;
    chip->PRAMDAC[0x0000050C/4]  = state->pllsel;
    chip->PRAMDAC[0x00000600/4]  = state->general;
    /*
     * Turn off VBlank enable and reset.
     */
//    *(chip->VBLANKENABLE) = 0;		/* FIXME*/
//    *(chip->VBLANK)       = chip->VBlankBit; /*FIXME*/
    /*
     * Set interrupt enable.
     */    
    chip->PMC[0x00000140/4]  = chip->EnableIRQ & 0x01;
    /*
     * Set current state pointer.
     */
    chip->CurrentState = state;
    /*
     * Reset FIFO free count.
     */
    chip->FifoFreeCount = 0;
}
static void UnloadStateExt