sis_300.c

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/* Recently Update by v1.09.50 */
#include <linux/config.h>
#include "sis_300.h"

#if defined(ALLOC_PRAGMA)
#pragma alloc_text(PAGE,SiSSetMode)
#pragma alloc_text(PAGE,SiSInit300)
#endif


#ifdef NOBIOS
BOOLEAN SiSInit300(PHW_DEVICE_EXTENSION HwDeviceExtension)
{
	ULONG	ROMAddr  = (ULONG)HwDeviceExtension->VirtualRomBase;
	ULONG	FBAddr	= (ULONG)HwDeviceExtension->VirtualVideoMemoryAddress;
	USHORT  BaseAddr = (USHORT)HwDeviceExtension->IOAddress;
	UCHAR	i,temp,AGP;
	ULONG	j,k,ulTemp;
	UCHAR	SR07,SR11,SR19,SR1A,SR1F,SR21,SR22,SR23,SR24,SR25,SR32;
	UCHAR	SR14;
	ULONG	Temp;

	if(ROMAddr==0)	return (FALSE);
	if(FBAddr==0)	 return (FALSE);
	if(BaseAddr==0)  return (FALSE);
	if(HwDeviceExtension->jChipID >= SIS_Trojan)
		if(!HwDeviceExtension->bIntegratedMMEnabled)  return (FALSE);

	P3c4=BaseAddr+0x14;
	P3d4=BaseAddr+0x24;
	P3c0=BaseAddr+0x10;
	P3ce=BaseAddr+0x1e;
	P3c2=BaseAddr+0x12;
	P3ca=BaseAddr+0x1a;
	P3c6=BaseAddr+0x16;
	P3c7=BaseAddr+0x17;
	P3c8=BaseAddr+0x18;
	P3c9=BaseAddr+0x19;
	P3da=BaseAddr+0x2A;
	Set_LVDS_TRUMPION();

	SetReg1(P3c4,0x05,0x86);	// 1.Openkey
	SR14 = (UCHAR)GetReg1(P3c4,0x14);
	SR19 = (UCHAR)GetReg1(P3c4,0x19);
	SR1A = (UCHAR)GetReg1(P3c4,0x1A);
	for(i=0x06;i< 0x20;i++) SetReg1(P3c4,i,0);	// 2.Reset Extended register
	for(i=0x21;i<=0x27;i++) SetReg1(P3c4,i,0);	//	Reset Extended register
	for(i=0x31;i<=0x3D;i++) SetReg1(P3c4,i,0);
	for(i=0x30;i<=0x37;i++) SetReg1(P3d4,i,0);

	if(HwDeviceExtension->jChipID >= SIS_Trojan)
		temp=(UCHAR)SR1A;		// 3.Set Define Extended register
	else
	{
		temp=*((UCHAR *)(ROMAddr+SoftSettingAddr));
		if((temp&SoftDRAMType)==0){					
			temp=(UCHAR)GetReg1(P3c4,0x3A);	// 3.Set Define Extended register
		}
	} 
	RAMType=temp&0x07;
	SetMemoryClock(ROMAddr);
	for(k=0; k<5; k++)
	{
		for(j=0; j<0xffff; j++)
		{
			ulTemp = (ULONG)GetReg1(P3c4, 0x05);
		}
	}
	Temp = (ULONG)GetReg1(P3c4, 0x3C);
	Temp = Temp | 0x01;
	SetReg1(P3c4, 0x3C, (USHORT)Temp);
	for(k=0; k<5; k++)
	{
		for(j=0; j<0xffff; j++)
		{
			Temp = (ULONG)GetReg1(P3c4, 0x05);
		}
	}
	Temp = (ULONG)GetReg1(P3c4, 0x3C);
	Temp = Temp & 0xFE;
	SetReg1(P3c4, 0x3C, (USHORT)Temp);
	for(k=0; k<5; k++)
	{
		for(j=0; j<0xffff; j++)
		{
			Temp = (ULONG)GetReg1(P3c4, 0x05);
		}
	}

	SR07=*((UCHAR *)(ROMAddr+0xA4));
	SetReg1(P3c4,0x07,SR07);
	if (HwDeviceExtension->jChipID == SIS_Glamour )
	{
		for(i=0x15;i<=0x1C;i++) 
		{
			temp=*((UCHAR *)(ROMAddr+0xA5+((i-0x15)*8)+RAMType));
			SetReg1(P3c4,i,temp);
		}
	}

	SR1F=*((UCHAR *)(ROMAddr+0xE5));
	SetReg1(P3c4,0x1F,SR1F);

	AGP=1;							// Get AGP
	temp=(UCHAR)GetReg1(P3c4,0x3A);
	temp=temp&0x30;
	if(temp==0x30) AGP=0;			// PCI

	SR21=*((UCHAR *)(ROMAddr+0xE6));
	if(AGP==0) SR21=SR21&0xEF;		// PCI
	SetReg1(P3c4,0x21,SR21);

	SR22=*((UCHAR *)(ROMAddr+0xE7));
	if(AGP==1) SR22=SR22&0x20;		// AGP
	SetReg1(P3c4,0x22,SR22);

	SR23=*((UCHAR *)(ROMAddr+0xE8));
	SetReg1(P3c4,0x23,SR23);

	SR24=*((UCHAR *)(ROMAddr+0xE9));
	SetReg1(P3c4,0x24,SR24);

	SR25=*((UCHAR *)(ROMAddr+0xEA));
	SetReg1(P3c4,0x25,SR25);

	SR32=*((UCHAR *)(ROMAddr+0xEB));
	SetReg1(P3c4,0x32,SR32);

	SR11=0x0F;
	SetReg1(P3c4,0x11,SR11);

	if(IF_DEF_LVDS==1){				//LVDS
		temp=ExtChipLVDS;
	}else if(IF_DEF_TRUMPION==1){ 	//Trumpion
		temp=ExtChipTrumpion;
	}else{ 			//301
		temp=ExtChip301;
	}
	SetReg1(P3d4,0x37,temp);

	//For SiS 630/540 Chip
	//Restore SR14, SR19 and SR1A
	SetReg1(P3c4,0x14,SR14);
	SetReg1(P3c4,0x19,SR19);
	SetReg1(P3c4,0x1A,SR1A);

	SetReg3(P3c6,0xff);		// Reset register
	ClearDAC(P3c8);			// Reset register
	DetectMonitor(HwDeviceExtension);	 //sense CRT1
	GetSenseStatus(HwDeviceExtension,BaseAddr,ROMAddr);//sense CRT2		
	
	return(TRUE);
}

VOID Set_LVDS_TRUMPION(VOID)
{
	IF_DEF_LVDS=0;
	IF_DEF_TRUMPION=0;	 
}

VOID SetMemoryClock(ULONG ROMAddr)
{
	UCHAR data,i;

	MCLKData=*((USHORT *)(ROMAddr+0x20C));		// MCLKData Table
	MCLKData=MCLKData+RAMType*5;
	ECLKData=MCLKData+0x28;

	for(i=0x28;i<=0x2A;i++) {					// Set MCLK
		data=*((UCHAR *)(ROMAddr+MCLKData));
		SetReg1(P3c4,i,data);
		MCLKData++;
	}

	for(i=0x2E;i<=0x30;i++) {					// Set ECLK
		data=*((UCHAR *)(ROMAddr+ECLKData));
		SetReg1(P3c4,i,data);
		ECLKData++;
	}
}
#endif   /* NOBIOS */

#ifdef CONFIG_FB_SIS_LINUXBIOS
BOOLEAN SiSInit300(PHW_DEVICE_EXTENSION HwDeviceExtension)
{
	ULONG	ROMAddr  = 0;
	USHORT  BaseAddr = (USHORT)HwDeviceExtension->IOAddress;
	UCHAR	i,temp,AGP;
	ULONG	j,k,ulTemp;
	UCHAR	SR07,SR11,SR19,SR1A,SR1F,SR21,SR22,SR23,SR24,SR25,SR32;
	UCHAR	SR14;
	ULONG	Temp;

	if(BaseAddr==0)  return (FALSE);
	if(HwDeviceExtension->jChipID >= SIS_Trojan)
		if(!HwDeviceExtension->bIntegratedMMEnabled)  return (FALSE);

	P3c4=BaseAddr+0x14;
	P3d4=BaseAddr+0x24;
	P3c0=BaseAddr+0x10;
	P3ce=BaseAddr+0x1e;
	P3c2=BaseAddr+0x12;
	P3ca=BaseAddr+0x1a;
	P3c6=BaseAddr+0x16;
	P3c7=BaseAddr+0x17;
	P3c8=BaseAddr+0x18;
	P3c9=BaseAddr+0x19;
	P3da=BaseAddr+0x2A;

	SetReg1(P3c4,0x05,0x86);	// 1.Openkey

	SR14 = (UCHAR)GetReg1(P3c4,0x14);
	SR19 = (UCHAR)GetReg1(P3c4,0x19);
	SR1A = (UCHAR)GetReg1(P3c4,0x1A);

	for(i=0x06;i< 0x20;i++) SetReg1(P3c4,i,0);	// 2.Reset Extended register
	for(i=0x21;i<=0x27;i++) SetReg1(P3c4,i,0);	//	Reset Extended register
	for(i=0x31;i<=0x3D;i++) SetReg1(P3c4,i,0);
	for(i=0x30;i<=0x37;i++) SetReg1(P3d4,i,0);

	temp=(UCHAR)SR1A;		// 3.Set Define Extended register

	RAMType=temp&0x07;
	SetMemoryClock(ROMAddr);
	for(k=0; k<5; k++)
		for(j=0; j<0xffff; j++)
			ulTemp = (ULONG)GetReg1(P3c4, 0x05);

	Temp = (ULONG)GetReg1(P3c4, 0x3C);
	Temp = Temp | 0x01;
	SetReg1(P3c4, 0x3C, (USHORT)Temp);

	for(k=0; k<5; k++)
		for(j=0; j<0xffff; j++)
			Temp = (ULONG)GetReg1(P3c4, 0x05);

	Temp = (ULONG)GetReg1(P3c4, 0x3C);
	Temp = Temp & 0xFE;
	SetReg1(P3c4, 0x3C, (USHORT)Temp);

	for(k=0; k<5; k++)
		for(j=0; j<0xffff; j++)
			Temp = (ULONG)GetReg1(P3c4, 0x05);

	SR07=SRegsInit[0x07];
	SetReg1(P3c4,0x07,SR07);

	SR1F=SRegsInit[0x1F];
	SetReg1(P3c4,0x1F,SR1F);

	AGP=1;							// Get AGP
	temp=(UCHAR)GetReg1(P3c4,0x3A);
	temp=temp&0x30;
	if(temp==0x30) AGP=0;			// PCI

	SR21=SRegsInit[0x21];
	if(AGP==0) SR21=SR21&0xEF;		// PCI
	SetReg1(P3c4,0x21,SR21);

	SR22=SRegsInit[0x22];
	if(AGP==1) SR22=SR22&0x20;		// AGP
	SetReg1(P3c4,0x22,SR22);

	SR23=SRegsInit[0x23];
	SetReg1(P3c4,0x23,SR23);

	SR24=SRegsInit[0x24];
	SetReg1(P3c4,0x24,SR24);

	SR25=SRegsInit[0x25];
	SetReg1(P3c4,0x25,SR25);

	SR32=SRegsInit[0x32];
	SetReg1(P3c4,0x32,SR32);

	SR11=0x0F;
	SetReg1(P3c4,0x11,SR11);

	temp=ExtChip301;
	SetReg1(P3d4,0x37,temp);

	SetReg1(P3c4,0x14,SR14);
	SetReg1(P3c4,0x19,SR19);
	SetReg1(P3c4,0x1A,SR1A);

	SetReg3(P3c6,0xff);		// Reset register
	ClearDAC(P3c8);			// Reset register
	DetectMonitor(HwDeviceExtension);	 //sense CRT1
	
	return(TRUE);
}

VOID SetMemoryClock(ULONG ROMAddr)
{
	UCHAR  i;
	USHORT idx;

	u8 MCLK[] = {
		0x5A, 0x64, 0x80, 0x66, 0x00,	// SDRAM
		0xB3, 0x45, 0x80, 0x83, 0x00,	// SGRAM
		0x37, 0x61, 0x80, 0x00, 0x01,	// ESDRAM
		0x37, 0x22, 0x80, 0x33, 0x01,
		0x37, 0x61, 0x80, 0x00, 0x01,
		0x37, 0x61, 0x80, 0x00, 0x01,
		0x37, 0x61, 0x80, 0x00, 0x01,
		0x37, 0x61, 0x80, 0x00, 0x01
	};

	u8 ECLK[] = {
		0x54, 0x43, 0x80, 0x00, 0x01,
		0x53, 0x43, 0x80, 0x00, 0x01,
		0x55, 0x43, 0x80, 0x00, 0x01,
		0x52, 0x43, 0x80, 0x00, 0x01,
		0x3f, 0x42, 0x80, 0x00, 0x01,
		0x54, 0x43, 0x80, 0x00, 0x01,
		0x54, 0x43, 0x80, 0x00, 0x01,
		0x54, 0x43, 0x80, 0x00, 0x01
	};

	idx = RAMType * 5;

	for (i = 0x28; i <= 0x2A; i++) {	// Set MCLK
		SetReg1(P3c4, i, MCLK[idx]);
		idx++;
	}

	idx = RAMType * 5;
	for (i = 0x2E; i <= 0x30; i++) {	// Set ECLK
		SetReg1(P3c4, i, ECLK[idx]);
		idx++;
	}

}

#endif   /* CONFIG_FB_SIS_LINUXBIOS */

// =========================================
// ======== SiS SetMode Function  ==========
// =========================================

#ifdef CONFIG_FB_SIS_LINUXBIOS
BOOLEAN SiSSetMode(PHW_DEVICE_EXTENSION HwDeviceExtension,
						 USHORT ModeNo)
{
	ULONG	i;
	USHORT  cr30flag,cr31flag;
	ULONG	ROMAddr  = (ULONG)HwDeviceExtension->VirtualRomBase;
	USHORT  BaseAddr = (USHORT)HwDeviceExtension->IOAddress;

	P3c4=BaseAddr+0x14;
	P3d4=BaseAddr+0x24;
	P3c0=BaseAddr+0x10;
	P3ce=BaseAddr+0x1e;
	P3c2=BaseAddr+0x12;
	P3ca=BaseAddr+0x1a;
	P3c6=BaseAddr+0x16;
	P3c7=BaseAddr+0x17;
	P3c8=BaseAddr+0x18;
	P3c9=BaseAddr+0x19;
	P3da=BaseAddr+0x2A;

	cr30flag=(UCHAR)GetReg1(P3d4,0x30);

	if(((cr30flag&0x01)==1)||((cr30flag&0x02)==0)){
		SetReg1(P3d4,0x34,ModeNo); 
		//SetSeqRegs(ROMAddr);
		{
			UCHAR SRdata;
			SRdata = SRegs[0x01] | 0x20;
			SetReg1(P3c4, 0x01, SRdata);

			for (i = 02; i <= 04; i++)
				SetReg1(P3c4, i, SRegs[i]);
		}

		//SetMiscRegs(ROMAddr);
		{
			SetReg3(P3c2, 0x23);
		}

		//SetCRTCRegs(ROMAddr);
		{
			UCHAR CRTCdata;

			CRTCdata = (UCHAR) GetReg1(P3d4, 0x11);
			SetReg1(P3d4, 0x11, CRTCdata);

			for (i = 0; i <= 0x18; i++)
				SetReg1(P3d4, i, CRegs[i]);
		}

		//SetATTRegs(ROMAddr);
		{
			for (i = 0; i <= 0x13; i++) {
				GetReg2(P3da);
				SetReg3(P3c0, i);
				SetReg3(P3c0, ARegs[i]);
			}
			GetReg2(P3da);
			SetReg3(P3c0, 0x14);
			SetReg3(P3c0, 0x00);
			GetReg2(P3da);
			SetReg3(P3c0, 0x20);
		}

		//SetGRCRegs(ROMAddr);
		{
			for (i = 0; i <= 0x08; i++)
				SetReg1(P3ce, i, GRegs[i]);
		}

		//ClearExt1Regs();
		{
			for (i = 0x0A; i <= 0x0E; i++)
				SetReg1(P3c4, i, 0x00);
		}


		//SetSync(ROMAddr);
		{
			SetReg3(P3c2, MReg);
		}

		//SetCRT1CRTC(ROMAddr);
		{
			UCHAR data;

			data = (UCHAR) GetReg1(P3d4, 0x11);
			data = data & 0x7F;
			SetReg1(P3d4, 0x11, data);

			for (i = 0; i <= 0x07; i++)
				SetReg1(P3d4, i, CRegs[i]);
			for (i = 0x10; i <= 0x12; i++)
				SetReg1(P3d4, i, CRegs[i]);
			for (i = 0x15; i <= 0x16; i++)
				SetReg1(P3d4, i, CRegs[i]);
			for (i = 0x0A; i <= 0x0C; i++)
				SetReg1(P3c4, i, SRegs[i]);

			data = SRegs[0x0E] & 0xE0;
			SetReg1(P3c4, 0x0E, data);

			SetReg1(P3d4, 0x09, CRegs[0x09]);
		}

		//SetCRT1Offset(ROMAddr);
		{
			SetReg1(P3c4, 0x0E, SRegs[0x0E]);
			SetReg1(P3c4, 0x10, SRegs[0x10]);
		}

		//SetCRT1VCLK(HwDeviceExtension, ROMAddr);
		{
			SetReg1(P3c4, 0x31, 0);

			for (i = 0x2B; i <= 0x2C; i++)
				SetReg1(P3c4, i, SRegs[i]);
			SetReg1(P3c4, 0x2D, 0x80);
		}

		//SetVCLKState(HwDeviceExtension, ROMAddr, ModeNo);
		{
			SetReg1(P3c4, 0x32, SRegs[0x32]);
			SetReg1(P3c4, 0x07, SRegs[0x07]);
		}

		//SetCRT1FIFO2(ROMAddr);
		{
			SetReg1(P3c4, 0x15, SRegs[0x15]);

			SetReg4(0xcf8, 0x80000050);
			SetReg4(0xcfc, 0xc5041e04);

			SetReg1(P3c4, 0x08, SRegs[0x08]);
			SetReg1(P3c4, 0x0F, SRegs[0x0F]);
			SetReg1(P3c4, 0x3b, 0x00);
			SetReg1(P3c4, 0x09, SRegs[0x09]);
		}

		//SetCRT1ModeRegs(ROMAddr, ModeNo);
		{
			SetReg1(P3c4, 0x06, SRegs[0x06]);
			SetReg1(P3c4, 0x01, SRegs[0x01]);
			SetReg1(P3c4, 0x0F, SRegs[0x0F]);
			SetReg1(P3c4, 0x21, SRegs[0x21]);
		}

		if(HwDeviceExtension->jChipID >= SIS_Trojan)
		{
			//SetInterlace(ROMAddr,ModeNo);
			SetReg1(P3d4, 0x19, CRegs[0x19]);
			SetReg1(P3d4, 0x1A, CRegs[0x1A]);
		}

		LoadDAC(ROMAddr);

		ClearBuffer(HwDeviceExtension);
	}

	cr31flag=(UCHAR)GetReg1(P3d4,0x31);
	DisplayOn();	// 16.DisplayOn
	return(NO_ERROR);
}

VOID LoadDAC(ULONG ROMAddr)
{
	USHORT data,data2;
	USHORT time,i,j,k;