dmfe.c

Linux内核源代码 为压缩文件 是<<Linux内核>>一书中的源代码

/*
   dmfe.c: Version 1.30 06/11/2000

   A Davicom DM9102(A)/DM9132/DM9801 fast ethernet driver for Linux. 
   Copyright (C) 1997  Sten Wang
   (C)Copyright 1997-1998 DAVICOM Semiconductor,Inc. All Rights Reserved.

   This program is free software; you can redistribute it and/or
   modify it under the terms of the GNU General Public License
   as published by the Free Software Foundation; either version 2
   of the License, or (at your option) any later version.

   This program is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.


   Compiler command:
   "gcc -DMODULE -D__KERNEL__ -I/usr/src/linux/net/inet -Wall 
   -Wstrict-prototypes -O6 -c dmfe.c"
   OR
   "gcc -DMODULE -D__KERNEL__ -I/usr/src/linux/net -Wall 
   -Wstrict-prototypes -O6 -c dmfe.c"

   The following steps teach you how to active DM9102 board:
   1. Used the upper compiler command to compile dmfe.c
   2. insert dmfe module into kernel
   "insmod dmfe"        ;;Auto Detection Mode
   "insmod dmfe mode=0" ;;Force 10M Half Duplex
   "insmod dmfe mode=1" ;;Force 100M Half Duplex
   "insmod dmfe mode=4" ;;Force 10M Full Duplex
   "insmod dmfe mode=5" ;;Force 100M Full Duplex
   3. config a dm9102 network interface
   "ifconfig eth0 172.22.3.18"
   4. active the IP routing table
   "route add -net 172.22.3.0 eth0"
   5. Well done. Your DM9102 adapter actived now.

   Author: Sten Wang, 886-3-5798797-8517, E-mail: [e-mail]

   Date:   10/28,1998

   (C)Copyright 1997-1998 DAVICOM Semiconductor, Inc. All Rights Reserved.

   Marcelo Tosatti <[e-mail]> : 
   Made it compile in 2.3 (device to net_device)
   
   Alan Cox <[e-mail]> :
   Cleaned up for kernel merge.
   Removed the back compatibility support
   Reformatted, fixing spelling etc as I went
   Removed IRQ 0-15 assumption

   Jeff Garzik <[e-mail]> :
   Updated to use new PCI driver API.
   Resource usage cleanups.
   Report driver version to user.

   TODO

   Implement pci_driver::suspend() and pci_driver::resume()
   power management methods.

   Check and fix on 64bit and big endian boxes.

   Test and make sure PCI latency is now correct for all cases.

 */

#define DMFE_VERSION "1.30 (June 11, 2000)"

#include <linux/module.h>

#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/string.h>
#include <linux/timer.h>
#include <linux/ptrace.h>
#include <linux/errno.h>
#include <linux/ioport.h>
#include <linux/malloc.h>
#include <linux/interrupt.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/version.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/skbuff.h>
#include <linux/delay.h>

#include <asm/processor.h>
#include <asm/bitops.h>
#include <asm/io.h>
#include <asm/dma.h>



/* Board/System/Debug information/definition ---------------- */
#define PCI_DM9132_ID   0x91321282	/* Davicom DM9132 ID */
#define PCI_DM9102_ID   0x91021282	/* Davicom DM9102 ID */
#define PCI_DM9100_ID   0x91001282	/* Davicom DM9100 ID */

#define DMFE_SUCC       0
#define DM9102_IO_SIZE  0x80
#define DM9102A_IO_SIZE 0x100
#define TX_FREE_DESC_CNT 0xc	/* Tx packet count */
#define TX_MAX_SEND_CNT 0x1	/* Maximum tx packet per time */
#define TX_DESC_CNT     0x10	/* Allocated Tx descriptors */
#define RX_DESC_CNT     0x10	/* Allocated Rx descriptors */
#define DESC_ALL_CNT    TX_DESC_CNT+RX_DESC_CNT
#define TX_BUF_ALLOC    0x600
#define RX_ALLOC_SIZE   0x620
#define DM910X_RESET    1
#define CR6_DEFAULT     0x00280000	/* SF, HD */
#define CR7_DEFAULT     0x1a2cd
#define CR15_DEFAULT    0x06	/* TxJabber RxWatchdog */
#define TDES0_ERR_MASK  0x4302	/* TXJT, LC, EC, FUE */
#define MAX_PACKET_SIZE 1514
#define DMFE_MAX_MULTICAST 14
#define RX_MAX_TRAFFIC  0x14000
#define MAX_CHECK_PACKET 0x8000

#define DMFE_10MHF      0
#define DMFE_100MHF     1
#define DMFE_10MFD      4
#define DMFE_100MFD     5
#define DMFE_AUTO       8

#define DMFE_TIMER_WUT  jiffies+(HZ*2)/2	/* timer wakeup time : 1 second */
#define DMFE_TX_TIMEOUT ((HZ*3)/2)	/* tx packet time-out time 1.5 s" */

#define DMFE_DBUG(dbug_now, msg, vaule) if (dmfe_debug || dbug_now) printk("DBUG: %s %x\n", msg, vaule)

#define DELAY_5US udelay(5)	/* udelay scale 1 usec */

#define DELAY_1US udelay(1)	/* udelay scale 1 usec */

#define SHOW_MEDIA_TYPE(mode) printk(KERN_WARNING "dmfe: Change Speed to %sMhz %s duplex\n",mode & 1 ?"100":"10", mode & 4 ? "full":"half");


/* CR9 definition: SROM/MII */
#define CR9_SROM_READ   0x4800
#define CR9_SRCS        0x1
#define CR9_SRCLK       0x2
#define CR9_CRDOUT      0x8
#define SROM_DATA_0     0x0
#define SROM_DATA_1     0x4
#define PHY_DATA_1      0x20000
#define PHY_DATA_0      0x00000
#define MDCLKH          0x10000

#define SROM_CLK_WRITE(data, ioaddr) outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr);DELAY_5US;outl(data|CR9_SROM_READ|CR9_SRCS|CR9_SRCLK,ioaddr);DELAY_5US;outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr);DELAY_5US;

#define __CHK_IO_SIZE(pci_id, dev_rev) ( ((pci_id)==PCI_DM9132_ID) || ((dev_rev) >= 0x02000030) ) ? DM9102A_IO_SIZE: DM9102_IO_SIZE
#define CHK_IO_SIZE(pci_dev, dev_rev) \
	__CHK_IO_SIZE(((pci_dev)->device << 16) | (pci_dev)->vendor, dev_rev)


/* Structure/enum declaration ------------------------------- */
struct tx_desc {
	u32 tdes0, tdes1, tdes2, tdes3;
	u32 tx_skb_ptr;
	u32 tx_buf_ptr;
	u32 next_tx_desc;
	u32 reserved;
};

struct rx_desc {
	u32 rdes0, rdes1, rdes2, rdes3;
	u32 rx_skb_ptr;
	u32 rx_buf_ptr;
	u32 next_rx_desc;
	u32 reserved;
};

struct dmfe_board_info {
	u32 chip_id;		/* Chip vendor/Device ID */
	u32 chip_revision;	/* Chip revision */
	struct net_device *next_dev;	/* next device */

	struct pci_dev *net_dev;	/* PCI device */

	unsigned long ioaddr;		/* I/O base address */
	u32 cr0_data;
	u32 cr5_data;
	u32 cr6_data;
	u32 cr7_data;
	u32 cr15_data;
	
	/* descriptor pointer */
	unsigned char *buf_pool_ptr;	/* Tx buffer pool memory */
	unsigned char *buf_pool_start;	/* Tx buffer pool align dword */
	unsigned char *desc_pool_ptr;	/* descriptor pool memory */
	struct tx_desc *first_tx_desc;
	struct tx_desc *tx_insert_ptr;
	struct tx_desc *tx_remove_ptr;
	struct rx_desc *first_rx_desc;
	struct rx_desc *rx_insert_ptr;
	struct rx_desc *rx_ready_ptr;	/* packet come pointer */
	u32 tx_packet_cnt;	/* transmitted packet count */
	u32 tx_queue_cnt;	/* wait to send packet count */
	u32 rx_avail_cnt;	/* available rx descriptor count */
	u32 interval_rx_cnt;	/* rx packet count a callback time */

	u16 phy_id2;		/* Phyxcer ID2 */

	u8 media_mode;		/* user specify media mode */
	u8 op_mode;		/* real work media mode */
	u8 phy_addr;
	u8 link_failed;		/* Ever link failed */
	u8 wait_reset;		/* Hardware failed, need to reset */
	u8 in_reset_state;	/* Now driver in reset routine */
	u8 rx_error_cnt;	/* recievd abnormal case count */
	u8 dm910x_chk_mode;	/* Operating mode check */
	struct timer_list timer;
	struct net_device_stats stats;	/* statistic counter */
	unsigned char srom[128];
};

enum dmfe_offsets {
	DCR0 = 0, DCR1 = 0x08, DCR2 = 0x10, DCR3 = 0x18, DCR4 = 0x20, DCR5 = 0x28,
	DCR6 = 0x30, DCR7 = 0x38, DCR8 = 0x40, DCR9 = 0x48, DCR10 = 0x50, DCR11 = 0x58,
	DCR12 = 0x60, DCR13 = 0x68, DCR14 = 0x70, DCR15 = 0x78
};

enum dmfe_CR6_bits {
	CR6_RXSC = 0x2, CR6_PBF = 0x8, CR6_PM = 0x40, CR6_PAM = 0x80, CR6_FDM = 0x200,
	CR6_TXSC = 0x2000, CR6_STI = 0x100000, CR6_SFT = 0x200000, CR6_RXA = 0x40000000,
	CR6_NO_PURGE = 0x20000000
};

/* Global variable declaration ----------------------------- */
static int dmfe_debug = 0;
static unsigned char dmfe_media_mode = 8;
static u32 dmfe_cr6_user_set = 0;

/* For module input parameter */
static int debug = 0;
static u32 cr6set = 0;
static unsigned char mode = 8;
static u8 chkmode = 1;

static unsigned long CrcTable[256] =
{
	0x00000000L, 0x77073096L, 0xEE0E612CL, 0x990951BAL,
	0x076DC419L, 0x706AF48FL, 0xE963A535L, 0x9E6495A3L,
	0x0EDB8832L, 0x79DCB8A4L, 0xE0D5E91EL, 0x97D2D988L,
	0x09B64C2BL, 0x7EB17CBDL, 0xE7B82D07L, 0x90BF1D91L,
	0x1DB71064L, 0x6AB020F2L, 0xF3B97148L, 0x84BE41DEL,
	0x1ADAD47DL, 0x6DDDE4EBL, 0xF4D4B551L, 0x83D385C7L,
	0x136C9856L, 0x646BA8C0L, 0xFD62F97AL, 0x8A65C9ECL,
	0x14015C4FL, 0x63066CD9L, 0xFA0F3D63L, 0x8D080DF5L,
	0x3B6E20C8L, 0x4C69105EL, 0xD56041E4L, 0xA2677172L,
	0x3C03E4D1L, 0x4B04D447L, 0xD20D85FDL, 0xA50AB56BL,
	0x35B5A8FAL, 0x42B2986CL, 0xDBBBC9D6L, 0xACBCF940L,
	0x32D86CE3L, 0x45DF5C75L, 0xDCD60DCFL, 0xABD13D59L,
	0x26D930ACL, 0x51DE003AL, 0xC8D75180L, 0xBFD06116L,
	0x21B4F4B5L, 0x56B3C423L, 0xCFBA9599L, 0xB8BDA50FL,
	0x2802B89EL, 0x5F058808L, 0xC60CD9B2L, 0xB10BE924L,
	0x2F6F7C87L, 0x58684C11L, 0xC1611DABL, 0xB6662D3DL,
	0x76DC4190L, 0x01DB7106L, 0x98D220BCL, 0xEFD5102AL,
	0x71B18589L, 0x06B6B51FL, 0x9FBFE4A5L, 0xE8B8D433L,
	0x7807C9A2L, 0x0F00F934L, 0x9609A88EL, 0xE10E9818L,
	0x7F6A0DBBL, 0x086D3D2DL, 0x91646C97L, 0xE6635C01L,
	0x6B6B51F4L, 0x1C6C6162L, 0x856530D8L, 0xF262004EL,
	0x6C0695EDL, 0x1B01A57BL, 0x8208F4C1L, 0xF50FC457L,
	0x65B0D9C6L, 0x12B7E950L, 0x8BBEB8EAL, 0xFCB9887CL,
	0x62DD1DDFL, 0x15DA2D49L, 0x8CD37CF3L, 0xFBD44C65L,
	0x4DB26158L, 0x3AB551CEL, 0xA3BC0074L, 0xD4BB30E2L,
	0x4ADFA541L, 0x3DD895D7L, 0xA4D1C46DL, 0xD3D6F4FBL,
	0x4369E96AL, 0x346ED9FCL, 0xAD678846L, 0xDA60B8D0L,
	0x44042D73L, 0x33031DE5L, 0xAA0A4C5FL, 0xDD0D7CC9L,
	0x5005713CL, 0x270241AAL, 0xBE0B1010L, 0xC90C2086L,
	0x5768B525L, 0x206F85B3L, 0xB966D409L, 0xCE61E49FL,
	0x5EDEF90EL, 0x29D9C998L, 0xB0D09822L, 0xC7D7A8B4L,
	0x59B33D17L, 0x2EB40D81L, 0xB7BD5C3BL, 0xC0BA6CADL,
	0xEDB88320L, 0x9ABFB3B6L, 0x03B6E20CL, 0x74B1D29AL,
	0xEAD54739L, 0x9DD277AFL, 0x04DB2615L, 0x73DC1683L,
	0xE3630B12L, 0x94643B84L, 0x0D6D6A3EL, 0x7A6A5AA8L,
	0xE40ECF0BL, 0x9309FF9DL, 0x0A00AE27L, 0x7D079EB1L,
	0xF00F9344L, 0x8708A3D2L, 0x1E01F268L, 0x6906C2FEL,
	0xF762575DL, 0x806567CBL, 0x196C3671L, 0x6E6B06E7L,
	0xFED41B76L, 0x89D32BE0L, 0x10DA7A5AL, 0x67DD4ACCL,
	0xF9B9DF6FL, 0x8EBEEFF9L, 0x17B7BE43L, 0x60B08ED5L,
	0xD6D6A3E8L, 0xA1D1937EL, 0x38D8C2C4L, 0x4FDFF252L,
	0xD1BB67F1L, 0xA6BC5767L, 0x3FB506DDL, 0x48B2364BL,
	0xD80D2BDAL, 0xAF0A1B4CL, 0x36034AF6L, 0x41047A60L,
	0xDF60EFC3L, 0xA867DF55L, 0x316E8EEFL, 0x4669BE79L,
	0xCB61B38CL, 0xBC66831AL, 0x256FD2A0L, 0x5268E236L,
	0xCC0C7795L, 0xBB0B4703L, 0x220216B9L, 0x5505262FL,
	0xC5BA3BBEL, 0xB2BD0B28L, 0x2BB45A92L, 0x5CB36A04L,
	0xC2D7FFA7L, 0xB5D0CF31L, 0x2CD99E8BL, 0x5BDEAE1DL,
	0x9B64C2B0L, 0xEC63F226L, 0x756AA39CL, 0x026D930AL,
	0x9C0906A9L, 0xEB0E363FL, 0x72076785L, 0x05005713L,
	0x95BF4A82L, 0xE2B87A14L, 0x7BB12BAEL, 0x0CB61B38L,
	0x92D28E9BL, 0xE5D5BE0DL, 0x7CDCEFB7L, 0x0BDBDF21L,
	0x86D3D2D4L, 0xF1D4E242L, 0x68DDB3F8L, 0x1FDA836EL,
	0x81BE16CDL, 0xF6B9265BL, 0x6FB077E1L, 0x18B74777L,
	0x88085AE6L, 0xFF0F6A70L, 0x66063BCAL, 0x11010B5CL,
	0x8F659EFFL, 0xF862AE69L, 0x616BFFD3L, 0x166CCF45L,
	0xA00AE278L, 0xD70DD2EEL, 0x4E048354L, 0x3903B3C2L,
	0xA7672661L, 0xD06016F7L, 0x4969474DL, 0x3E6E77DBL,
	0xAED16A4AL, 0xD9D65ADCL, 0x40DF0B66L, 0x37D83BF0L,
	0xA9BCAE53L, 0xDEBB9EC5L, 0x47B2CF7FL, 0x30B5FFE9L,
	0xBDBDF21CL, 0xCABAC28AL, 0x53B39330L, 0x24B4A3A6L,
	0xBAD03605L, 0xCDD70693L, 0x54DE5729L, 0x23D967BFL,
	0xB3667A2EL, 0xC4614AB8L, 0x5D681B02L, 0x2A6F2B94L,
	0xB40BBE37L, 0xC30C8EA1L, 0x5A05DF1BL, 0x2D02EF8DL
};

/* function declaration ------------------------------------- */
static int dmfe_open(struct net_device *);
static int dmfe_start_xmit(struct sk_buff *, struct net_device *);
static int dmfe_stop(struct net_device *);
static struct net_device_stats *dmfe_get_stats(struct net_device *);
static void dmfe_set_filter_mode(struct net_device *);
static int dmfe_do_ioctl(struct net_device *, struct ifreq *, int);
static u16 read_srom_word(long, int);
static void dmfe_interrupt(int, void *, struct pt_regs *);
static void dmfe_descriptor_init(struct dmfe_board_info *, u32);
static void allocated_rx_buffer(struct dmfe_board_info *);
static void update_cr6(u32, u32);
static void send_filter_frame(struct net_device *, int);
static void dm9132_id_table(struct net_device *, int);
static u16 phy_read(u32, u8, u8, u32);
static void phy_write(u32, u8, u8, u16, u32);
static void phy_write_1bit(u32, u32);
static u16 phy_read_1bit(u32);
static void dmfe_sense_speed(struct dmfe_board_info *);
static void dmfe_process_mode(struct dmfe_board_info *);
static void dmfe_timer(unsigned long);
static void dmfe_rx_packet(struct net_device *, struct dmfe_board_info *);
static void dmfe_reused_skb(struct dmfe_board_info *, struct sk_buff *);
static void dmfe_dynamic_reset(struct net_device *);
static void dmfe_free_rxbuffer(struct dmfe_board_info *);
static void dmfe_init_dm910x(struct net_device *);
static unsigned long cal_CRC(unsigned char *, unsigned int, u8);

/* DM910X network board routine ---------------------------- */

/*
 *	Search DM910X board, allocate space and register it
 */
 

static int __init dmfe_init_one (struct pci_dev *pdev,
				 const struct pci_device_id *ent)
{
	unsigned long pci_iobase;
	u8 pci_irqline;
	struct dmfe_board_info *db;	/* Point a board information structure */
	int i;
	struct net_device *dev;
	u32 dev_rev;

	DMFE_DBUG(0, "dmfe_probe()", 0);

	pci_iobase = pci_resource_start(pdev, 0);
	pci_irqline = pdev->irq;

	/* Interrupt check */
	if (pci_irqline == 0) {
		printk(KERN_ERR "dmfe: Interrupt wrong : IRQ=%d\n",
		       pci_irqline);
		goto err_out;
	}

	/* iobase check */
	if (pci_iobase == 0) {
		printk(KERN_ERR "dmfe: I/O base is zero\n");
		goto err_out;
	}

	/* Enable Master/IO access, Disable memory access */
	if (pci_enable_device(pdev))
		goto err_out;
	pci_set_master(pdev);

#if 0	/* pci_{enable_device,set_master} sets minimum latency for us now */

	/* Set Latency Timer 80h */
	/* FIXME: setting values > 32 breaks some SiS 559x stuff.
	   Need a PCI quirk.. */

	pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x80);
#endif

	/* Read Chip revision */
	pci_read_config_dword(pdev, PCI_REVISION_ID, &dev_rev);

	/* Init network device */
	dev = init_etherdev(NULL, sizeof(*db));
	if (dev == NULL)
		goto err_out;
	SET_MODULE_OWNER(dev);

	/* IO range check */
	if (!request_region(pci_iobase, CHK_IO_SIZE(pdev, dev_rev), dev->name)) {
		printk(KERN_ERR "dmfe: I/O conflict : IO=%lx Range=%x\n",
		       pci_iobase, CHK_IO_SIZE(pdev, dev_rev));
		goto err_out_netdev;
	}

	db = dev->priv;
	pdev->driver_data = dev;

	db->chip_id = ent->driver_data;
	db->ioaddr = pci_iobase;
	db->chip_revision = dev_rev;

	db->net_dev = pdev;

	dev->base_addr = pci_iobase;
	dev->irq = pci_irqline;
	dev->open = &dmfe_open;
	dev->hard_start_xmit = &dmfe_start_xmit;
	dev->stop = &dmfe_stop;
	dev->get_stats = &dmfe_get_stats;
	dev->set_multicast_list = &dmfe_set_filter_mode;
	dev->do_ioctl = &dmfe_do_ioctl;

	/* read 64 word srom data */
	for (i = 0; i < 64; i++)
		((u16 *) db->srom)[i] = read_srom_word(pci_iobase, i);

	/* Set Node address */
	for (i = 0; i < 6; i++)
		dev->dev_addr[i] = db->srom[20 + i];

	return 0;

err_out_netdev:
	unregister_netdev(dev);
	kfree(dev);
err_out:
	return -ENODEV;
}


static void __exit dmfe_remove_one (struct pci_dev *pdev)
{
	struct net_device *dev = pdev->driver_data;
	struct dmfe_board_info *db;

	DMFE_DBUG(0, "dmfe_remove_one()", 0);
	
	db = dev->priv;

	unregister_netdev(dev);
	release_region(dev->base_addr, CHK_IO_SIZE(pdev, db->chip_revision));
	kfree(dev);	/* free board information */

	DMFE_DBUG(0, "dmfe_remove_one() exit", 0);
}


/*
 *	Open the interface.
 *	The interface is opened whenever "ifconfig" actives it.
 */
 
static int dmfe_open(struct net_device *dev)
{
	int ret;
	struct dmfe_board_info *db = dev->priv;

	DMFE_DBUG(0, "dmfe_open", 0);

	ret = request_irq(dev->irq, &dmfe_interrupt, SA_SHIRQ, dev->name, dev);
	if (ret)
		return ret;

	/* Allocated Tx/Rx descriptor memory */
	db->desc_pool_ptr = kmalloc(sizeof(struct tx_desc) * DESC_ALL_CNT + 0x20, GFP_KERNEL | GFP_DMA);
	if (db->desc_pool_ptr == NULL)
		return -ENOMEM;
	if ((u32) db->desc_pool_ptr & 0x1f)
		db->first_tx_desc = (struct tx_desc *) (((u32) db->desc_pool_ptr & ~0x1f) + 0x20);
	else
		db->first_tx_desc = (struct tx_desc *) db->desc_pool_ptr;

	/* Allocated Tx buffer memory */
	db->buf_pool_ptr = kmalloc(TX_BUF_ALLOC * TX_DESC_CNT + 4, GFP_KERNEL | GFP_DMA);
	if (db->buf_pool_ptr == NULL) {
		kfree(db->desc_pool_ptr);
		return -ENOMEM;
	}
	if ((u32) db->buf_pool_ptr & 0x3)
		db->buf_pool_start = (char *) (((u32) db->buf_pool_ptr & ~0x3) + 0x4);
	else
		db->buf_pool_start = db->buf_pool_ptr;

	/* system variable init */
	db->cr6_data = CR6_DEFAULT | dmfe_cr6_user_set;
	db->tx_packet_cnt = 0;
	db->tx_queue_cnt = 0;
	db->rx_avail_cnt = 0;
	db->link_failed = 0;
	db->wait_reset = 0;
	db->in_reset_state = 0;
	db->rx_error_cnt = 0;

	if (!chkmode || (db->chip_id == PCI_DM9132_ID) || (db->chip_revision >= 0x02000030)) {
		//db->cr6_data &= ~CR6_SFT;         /* Used Tx threshold */
		//db->cr6_data |= CR6_NO_PURGE;     /* No purge if rx unavailable */
		db->cr0_data = 0xc00000;	/* TX/RX desc burst mode */
		db->dm910x_chk_mode = 4;	/* Enter the normal mode */
	} else {
		db->cr0_data = 0;
		db->dm910x_chk_mode = 1;	/* Enter the check mode */
	}

	/* Initilize DM910X board */
	dmfe_init_dm910x(dev);

	/* set and active a timer process */
	init_timer(&db->timer);
	db->timer.expires = DMFE_TIMER_WUT;
	db->timer.data = (unsigned long) dev;
	db->timer.function = &dmfe_timer;
	add_timer(&db->timer);
	
	netif_wake_queue(dev);

	return 0;
}

/* Initilize DM910X board
   Reset DM910X board
   Initilize TX/Rx descriptor chain structure
   Send the set-up frame
   Enable Tx/Rx machine
 */
static void dmfe_init_dm910x(struct net_device *dev)
{
	struct dmfe_board_info *db = dev->priv;
	u32 ioaddr = db->ioaddr;

	DMFE_DBUG(0, "dmfe_init_dm910x()", 0);