gmac.h

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/* -- 60b0		MAC address filter mask 1,2
 */
#define GM_MAC_ADDR_FILTER_MASK1_2	(0x60b0 | REG_SZ_8)

/* -- 60b4		MAC address filter mask 0
 */
#define GM_MAC_ADDR_FILTER_MASK0	(0x60b4 | REG_SZ_16)

/* -- [60c0 .. 60fc]	MAC hash table
 */
#define GM_MAC_ADDR_FILTER_HASH0	(0x60c0 | REG_SZ_16)

/* -- 6100		MAC normal collision counter
 */
#define GM_MAC_COLLISION_CTR		(0x6100 | REG_SZ_16)

/* -- 6104		MAC 1st successful collision counter
 */
#define GM_MAC_FIRST_COLLISION_CTR	(0x6104 | REG_SZ_16)

/* -- 6108		MAC excess collision counter
 */
#define GM_MAC_EXCS_COLLISION_CTR	(0x6108 | REG_SZ_16)

/* -- 610c		MAC late collision counter
 */
#define GM_MAC_LATE_COLLISION_CTR	(0x610c | REG_SZ_16)

/* -- 6110		MAC defer timer counter
 */
#define GM_MAC_DEFER_TIMER_COUNTER	(0x6110 | REG_SZ_16)

/* -- 6114		MAC peak attempts
 */
#define GM_MAC_PEAK_ATTEMPTS		(0x6114 | REG_SZ_16)

/* -- 6118		MAC Rx frame counter
 */
#define GM_MAC_RX_FRAME_CTR		(0x6118 | REG_SZ_16)

/* -- 611c		MAC Rx length error counter
 */
#define GM_MAC_RX_LEN_ERR_CTR		(0x611c | REG_SZ_16)

/* -- 6120		MAC Rx alignment error counter
 */
#define GM_MAC_RX_ALIGN_ERR_CTR		(0x6120 | REG_SZ_16)

/* -- 6124		MAC Rx CRC error counter
 */
#define GM_MAC_RX_CRC_ERR_CTR		(0x6124 | REG_SZ_16)

/* -- 6128		MAC Rx code violation error counter
 */
#define GM_MAC_RX_CODE_VIOLATION_CTR	(0x6128 | REG_SZ_16)

/* -- 6130		MAC random number seed
 */
#define GM_MAC_RANDOM_SEED		(0x6130 | REG_SZ_16)

/* -- 6134		MAC state machine
 */
#define GM_MAC_STATE_MACHINE		(0x6134 | REG_SZ_8)


	/*
	 * MIF registers
	 */


/* -- 0x6200	RW	MIF bit bang clock
 */
#define GM_MIF_BB_CLOCK			(0x6200 | REG_SZ_8)

/* -- 0x6204	RW	MIF bit bang data
 */
#define GM_MIF_BB_DATA			(0x6204 | REG_SZ_8)

/* -- 0x6208	RW	MIF bit bang output enable
 */
#define GM_MIF_BB_OUT_ENABLE		(0x6208 | REG_SZ_8)

/* -- 0x620c	RW	MIF frame control & data
 */
#define GM_MIF_FRAME_CTL_DATA		(0x620c | REG_SZ_32)
#define GM_MIF_FRAME_START_MASK		0xc0000000
#define GM_MIF_FRAME_START_SHIFT	30
#define GM_MIF_FRAME_OPCODE_MASK	0x30000000
#define GM_MIF_FRAME_OPCODE_SHIFT	28
#define GM_MIF_FRAME_PHY_ADDR_MASK	0x0f800000
#define GM_MIF_FRAME_PHY_ADDR_SHIFT	23
#define GM_MIF_FRAME_REG_ADDR_MASK	0x007c0000
#define GM_MIF_FRAME_REG_ADDR_SHIFT	18
#define GM_MIF_FRAME_TURNAROUND_HI	0x00020000
#define GM_MIF_FRAME_TURNAROUND_LO	0x00010000
#define GM_MIF_FRAME_DATA_MASK		0x0000ffff
#define GM_MIF_FRAME_DATA_SHIFT		0

/* -- 0x6210	RW	MIF config reg
 */
#define GM_MIF_CFG			(0x6210 | REG_SZ_16)
#define	GM_MIF_CFGPS			0x00000001	/* PHY Select */
#define	GM_MIF_CFGPE			0x00000002	/* Poll Enable */
#define	GM_MIF_CFGBB			0x00000004	/* Bit Bang Enable */
#define	GM_MIF_CFGPR_MASK		0x000000f8	/* Poll Register address */
#define	GM_MIF_CFGPR_SHIFT		3
#define	GM_MIF_CFGM0			0x00000100	/* MDIO_0 Data / MDIO_0 attached */
#define	GM_MIF_CFGM1			0x00000200	/* MDIO_1 Data / MDIO_1 attached */
#define	GM_MIF_CFGPD_MASK		0x00007c00	/* Poll Device PHY address */
#define	GM_MIF_CFGPD_SHIFT		10

#define	GM_MIF_POLL_DELAY		200

#define	GM_INTERNAL_PHYAD		1		/* PHY address for int. transceiver */
#define	GM_EXTERNAL_PHYAD		0		/* PHY address for ext. transceiver */

/* -- 0x6214	RW	MIF interrupt mask reg
 *			same as basic/status Register
 */
#define GM_MIF_IRQ_MASK			(0x6214 | REG_SZ_16)

/* -- 0x6218	RW	MIF basic/status reg
 *			The Basic portion of this register indicates the last
 *			value of the register read indicated in the POLL REG field
 *			of the Configuration Register.
 *			The Status portion indicates bit(s) that have changed.
 *			The MIF Mask register is corresponding to this register in
 *			terms of the bit(s) that need to be masked for generating
 *			interrupt on the MIF Interrupt Bit of the Global Status Rgister.
 */
#define GM_MIF_STATUS			(0x6218 | REG_SZ_32)

#define	GM_MIF_STATUS_MASK		0x0000ffff	/* 0-15 : Status */
#define	GM_MIF_BASIC_MASK		0xffff0000	/* 16-31 : Basic register */

	/*
	 * PCS link registers
	 */

/* -- 0x9000	RW	PCS mii control reg
 */
#define GM_PCS_CONTROL			(0x9000 | REG_SZ_16)

/* -- 0x9004	RW	PCS mii status reg
 */
#define GM_PCS_STATUS			(0x9004 | REG_SZ_16)

/* -- 0x9008	RW	PCS mii advertisement
 */
#define GM_PCS_ADVERTISEMENT		(0x9008 | REG_SZ_16)

/* -- 0x900c	RW	PCS mii LP ability
 */
#define GM_PCS_ABILITY			(0x900c | REG_SZ_16)

/* -- 0x9010	RW	PCS config
 */
#define GM_PCS_CONFIG			(0x9010 | REG_SZ_8)

/* -- 0x9014	RW	PCS state machine
 */
#define GM_PCS_STATE_MACHINE		(0x9014 | REG_SZ_32)

/* -- 0x9018	RW	PCS interrupt status
 */
#define GM_PCS_IRQ_STATUS		(0x9018 | REG_SZ_8)

/* -- 0x9050	RW	PCS datapath mode
 */
#define GM_PCS_DATAPATH_MODE		(0x9050 | REG_SZ_8)
#define GM_PCS_DATAPATH_INTERNAL	0x01	/* Internal serial link */
#define GM_PCS_DATAPATH_SERDES		0x02	/* 10-bit Serdes interface */
#define GM_PCS_DATAPATH_MII		0x04	/* Select mii/gmii mode */
#define GM_PCS_DATAPATH_GMII_OUT	0x08	/* serial mode only, copy data to gmii */

/* -- 0x9054	RW	PCS serdes control
 */
#define GM_PCS_SERDES_CTRL		(0x9054 | REG_SZ_8)

/* -- 0x9058	RW	PCS serdes output select
 */
#define GM_PCS_SERDES_SELECT		(0x9058 | REG_SZ_8)

/* -- 0x905c	RW	PCS serdes state
 */
#define GM_PCS_SERDES_STATE		(0x905c | REG_SZ_8)


	/*
	 * PHY registers
	 */

/*
 * Standard PHY registers (from de4x5.h)
 */
#define MII_CR       0x00          /* MII Management Control Register */
#define MII_SR       0x01          /* MII Management Status Register */
#define MII_ID0      0x02          /* PHY Identifier Register 0 */
#define MII_ID1      0x03          /* PHY Identifier Register 1 */
#define MII_ANA      0x04          /* Auto Negotiation Advertisement */
#define MII_ANLPA    0x05          /* Auto Negotiation Link Partner Ability */
#define MII_ANE      0x06          /* Auto Negotiation Expansion */
#define MII_ANP      0x07          /* Auto Negotiation Next Page TX */

/*
** MII Management Control Register
*/
#define MII_CR_RST  0x8000         /* RESET the PHY chip */
#define MII_CR_LPBK 0x4000         /* Loopback enable */
#define MII_CR_SPD  0x2000         /* 0: 10Mb/s; 1: 100Mb/s */
#define MII_CR_10   0x0000         /* Set 10Mb/s */
#define MII_CR_100  0x2000         /* Set 100Mb/s */
#define MII_CR_ASSE 0x1000         /* Auto Speed Select Enable */
#define MII_CR_PD   0x0800         /* Power Down */
#define MII_CR_ISOL 0x0400         /* Isolate Mode */
#define MII_CR_RAN  0x0200         /* Restart Auto Negotiation */
#define MII_CR_FDM  0x0100         /* Full Duplex Mode */
#define MII_CR_CTE  0x0080         /* Collision Test Enable */

/*
** MII Management Status Register
*/
#define MII_SR_T4C  0x8000         /* 100BASE-T4 capable */
#define MII_SR_TXFD 0x4000         /* 100BASE-TX Full Duplex capable */
#define MII_SR_TXHD 0x2000         /* 100BASE-TX Half Duplex capable */
#define MII_SR_TFD  0x1000         /* 10BASE-T Full Duplex capable */
#define MII_SR_THD  0x0800         /* 10BASE-T Half Duplex capable */
#define MII_SR_ASSC 0x0020         /* Auto Speed Selection Complete*/
#define MII_SR_RFD  0x0010         /* Remote Fault Detected */
#define MII_SR_ANC  0x0008         /* Auto Negotiation capable */
#define MII_SR_LKS  0x0004         /* Link Status */
#define MII_SR_JABD 0x0002         /* Jabber Detect */
#define MII_SR_XC   0x0001         /* Extended Capabilities */

/*
** MII Management Auto Negotiation Advertisement Register
*/
#define MII_ANA_TAF  0x03e0        /* Technology Ability Field */
#define MII_ANA_T4AM 0x0200        /* T4 Technology Ability Mask */
#define MII_ANA_TXAM 0x0180        /* TX Technology Ability Mask */
#define MII_ANA_FDAM 0x0140        /* Full Duplex Technology Ability Mask */
#define MII_ANA_HDAM 0x02a0        /* Half Duplex Technology Ability Mask */
#define MII_ANA_100M 0x0380        /* 100Mb Technology Ability Mask */
#define MII_ANA_10M  0x0060        /* 10Mb Technology Ability Mask */
#define MII_ANA_CSMA 0x0001        /* CSMA-CD Capable */

/*
** MII Management Auto Negotiation Remote End Register
*/
#define MII_ANLPA_NP   0x8000      /* Next Page (Enable) */
#define MII_ANLPA_ACK  0x4000      /* Remote Acknowledge */
#define MII_ANLPA_RF   0x2000      /* Remote Fault */
#define MII_ANLPA_TAF  0x03e0      /* Technology Ability Field */
#define MII_ANLPA_T4AM 0x0200      /* T4 Technology Ability Mask */
#define MII_ANLPA_TXAM 0x0180      /* TX Technology Ability Mask */
#define MII_ANLPA_FDAM 0x0140      /* Full Duplex Technology Ability Mask */
#define MII_ANLPA_HDAM 0x02a0      /* Half Duplex Technology Ability Mask */
#define MII_ANLPA_100M 0x0380      /* 100Mb Technology Ability Mask */
#define MII_ANLPA_10M  0x0060      /* 10Mb Technology Ability Mask */
#define MII_ANLPA_CSMA 0x0001      /* CSMA-CD Capable */
#define MII_ANLPA_PAUS 0x0400 

/*
 * Model-specific PHY registers
 *
 * Note: Only the BCM5201 is described here for now. I'll add the 5400 once
 *       I see a machine using it in real world.
 */

/* Supported PHYs (phy_type field ) */
#define PHY_B5400	0x5400
#define PHY_B5201	0x5201
#define PHY_LXT971	0x0971
#define PHY_UNKNOWN	0

/* Identification (for multi-PHY) */
#define MII_BCM5201_OUI                         0x001018
#define MII_BCM5201_MODEL                       0x21
#define MII_BCM5201_REV                         0x01
#define MII_BCM5201_ID                          ((MII_BCM5201_OUI << 10) | (MII_BCM5201_MODEL << 4))
#define MII_BCM5201_MASK                        0xfffffff0
#define MII_BCM5400_OUI                         0x000818
#define MII_BCM5400_MODEL                       0x04
#define MII_BCM5400_REV                         0x01
#define MII_BCM5400_ID                          ((MII_BCM5400_OUI << 10) | (MII_BCM5400_MODEL << 4))
#define MII_BCM5400_MASK                        0xfffffff0
#define MII_LXT971_OUI                          0x0004de
#define MII_LXT971_MODEL                        0x0e
#define MII_LXT971_REV                          0x00
#define MII_LXT971_ID                           ((MII_LXT971_OUI << 10) | (MII_LXT971_MODEL << 4))
#define MII_LXT971_MASK                         0xfffffff0

/* BCM5201 AUX STATUS register */
#define MII_BCM5201_AUXCTLSTATUS		0x18
#define MII_BCM5201_AUXCTLSTATUS_DUPLEX		0x0001
#define MII_BCM5201_AUXCTLSTATUS_SPEED		0x0002

/* MII BCM5201 MULTIPHY interrupt register */
#define MII_BCM5201_INTERRUPT			0x1A
#define MII_BCM5201_INTERRUPT_INTENABLE		0x4000

#define MII_BCM5201_AUXMODE2			0x1B
#define MII_BCM5201_AUXMODE2_LOWPOWER		0x0008

#define MII_BCM5201_MULTIPHY                    0x1E

/* MII BCM5201 MULTIPHY register bits */
#define MII_BCM5201_MULTIPHY_SERIALMODE         0x0002
#define MII_BCM5201_MULTIPHY_SUPERISOLATE       0x0008

/* MII BCM5400 1000-BASET Control register */
#define MII_BCM5400_GB_CONTROL			0x09
#define MII_BCM5400_GB_CONTROL_FULLDUPLEXCAP	0x0200

/* MII BCM5400 AUXCONTROL register */
#define MII_BCM5400_AUXCONTROL                  0x18
#define MII_BCM5400_AUXCONTROL_PWR10BASET       0x0004

/* MII BCM5400 AUXSTATUS register */
#define MII_BCM5400_AUXSTATUS                   0x19
#define MII_BCM5400_AUXSTATUS_LINKMODE_MASK     0x0700
#define MII_BCM5400_AUXSTATUS_LINKMODE_SHIFT    8  

/* MII LXT971 STATUS2 register */
#define MII_LXT971_STATUS2			0x11
#define MII_LXT971_STATUS2_SPEED		0x4000
#define MII_LXT971_STATUS2_LINK			0x0400
#define MII_LXT971_STATUS2_FULLDUPLEX		0x0200
#define MII_LXT971_STATUS2_AUTONEG_COMPLETE	0x0080



	/*
	 * DMA descriptors
	 */


/* 
 * Descriptor counts and buffer sizes
 */
#define NTX			64		/* must be power of 2 */
#define NTX_CONF		GM_TX_RING_SZ_64
#define NRX			64		/* must be power of 2 */
#define NRX_CONF		GM_RX_RING_SZ_64
#define RX_COPY_THRESHOLD	256
#define GMAC_BUFFER_ALIGN	32		/* Align on a cache line */
#define RX_BUF_ALLOC_SIZE	(ETH_FRAME_LEN + GMAC_BUFFER_ALIGN + 2)
#define RX_OFFSET		2

/*
 * Definitions of Rx and Tx descriptors
 */

struct gmac_dma_desc {
	unsigned int	size;		/* data size and OWN bit */
	unsigned int	flags;		/* flags */
	unsigned int	lo_addr;	/* phys addr, low 32 bits */
	unsigned int	hi_addr;
};

/*
 * Rx bits
 */
 
/* Bits in size */
#define RX_SZ_OWN		0x80000000	/* 1 = owned by chip */
#define RX_SZ_MASK		0x7FFF0000
#define RX_SZ_SHIFT		16
#define RX_SZ_CKSUM_MASK	0x0000FFFF

/* Bits in flags */
#define RX_FL_CRC_ERROR		0x40000000
#define RX_FL_ALT_ADDR		0x20000000	/* Packet rcv. from alt MAC address */

/* 
 * Tx bits
 */

/* Bits in size */
#define TX_SZ_MASK		0x00007FFF
#define TX_SZ_CRC_MASK		0x00FF8000
#define TX_SZ_CRC_STUFF		0x1F000000
#define TX_SZ_CRC_ENABLE	0x20000000
#define TX_SZ_EOP		0x40000000
#define TX_SZ_SOP		0x80000000
/* Bits in flags */
#define TX_FL_INTERRUPT		0x00000001
#define TX_FL_NO_CRC		0x00000002

	/*
	 * Other stuffs
	 */
	 
struct gmac {
	volatile unsigned int		*regs;	/* hardware registers, virtual addr */
	struct net_device		*dev;
	struct device_node		*of_node;
	unsigned long			tx_desc_page;	/* page for DMA descriptors */
	unsigned long			rx_desc_page;	/* page for DMA descriptors */
	volatile struct			gmac_dma_desc *rxring;
	struct sk_buff			*rx_buff[NRX];
	int				next_rx;
	volatile struct	gmac_dma_desc	*txring;
	struct sk_buff			*tx_buff[NTX];
	int				next_tx;
	int				tx_gone;
	int				phy_addr;
	unsigned int			phy_id;
	int				phy_type;
	int				phy_status;	/* Cached PHY status */
	int				full_duplex;	/* Current set to full duplex */
	int				gigabit;	/* Current set to 1000BT */
	struct net_device_stats		stats;
	u8				pci_bus;
	u8				pci_devfn;
	spinlock_t			lock;
	int				opened;
	struct net_device		*next_gmac;
};


/* Register access macros. We hope the preprocessor will be smart enough
 * to optimize them into one single access instruction
 */
#define GM_OUT(reg, v)		(((reg) & REG_SZ_32) ? out_le32(gm->regs + \
					(((reg) & REG_MASK)>>2), (v))  \
				: (((reg) & REG_SZ_16) ? out_le16((volatile u16 *) \
					(gm->regs + (((reg) & REG_MASK)>>2)), (v))  \
				: out_8((volatile u8 *)(gm->regs + \
					(((reg) & REG_MASK)>>2)), (v))))
#define GM_IN(reg)		(((reg) & REG_SZ_32) ? in_le32(gm->regs + \
					(((reg) & REG_MASK)>>2))  \
				: (((reg) & REG_SZ_16) ? in_le16((volatile u16 *) \
					(gm->regs + (((reg) & REG_MASK)>>2)))  \
				: in_8((volatile u8 *)(gm->regs + \
					(((reg) & REG_MASK)>>2)))))
#define GM_BIS(r, v)		GM_OUT((r), GM_IN(r) | (v))
#define GM_BIC(r, v)		GM_OUT((r), GM_IN(r) & ~(v))

/* Wrapper to alloc_skb to test various alignements */
#define GMAC_ALIGNED_RX_SKB_ADDR(addr) \
        ((((unsigned long)(addr) + GMAC_BUFFER_ALIGN - 1) & \
        ~(GMAC_BUFFER_ALIGN - 1)) - (unsigned long)(addr))
        
static inline struct sk_buff *
gmac_alloc_skb(unsigned int length, int gfp_flags)
{
	struct sk_buff *skb;

	skb = alloc_skb(length + GMAC_BUFFER_ALIGN, gfp_flags);
	if(skb) {
		int offset = GMAC_ALIGNED_RX_SKB_ADDR(skb->data);

		if(offset)
			skb_reserve(skb, offset);
	}
	return skb;
}