aironet4500.h

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/*
 *	 Aironet 4500 Pcmcia driver
 *
 *		Elmer Joandi, Januar 1999
 *	Copyright:	GPL
 *	
 *
 *	Revision 0.1 ,started  30.12.1998
 *
 *
 */
 

#ifndef AIRONET4500_H
#define	AIRONET4500_H
// redefined to avoid PCMCIA includes

 #include <linux/version.h>
/*#include <linux/module.h>
 #include <linux/kernel.h>
*/

/*
#include <linux/types.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/delay.h>
#include <linux/time.h>
*/
#include <linux/802_11.h>

//damn idiot PCMCIA stuff
#ifndef DEV_NAME_LEN
	#define DEV_NAME_LEN 32
#endif

struct pcmcia_junkdev_node_t {
    char		dev_name[DEV_NAME_LEN];
    u_short		major, minor;
    struct dev_node_t	*next;
};

#ifndef CS_RELEASE
typedef struct pcmcia_junkdev_node_t dev_node_t;
#endif



#include <linux/spinlock.h>
typedef spinlock_t 			my_spinlock_t	;
#define my_spin_lock_init(a)		spin_lock_init(a)
#define my_spin_lock_irqsave(a,b) 	spin_lock_irqsave(a,b)
#define my_spin_unlock_irqrestore(a,b) 	spin_unlock_irqrestore(a,b)


#define AWC_ERROR	-1
#define AWC_SUCCESS	0

struct awc_cis {
	unsigned char cis[0x301];
	unsigned char unknown302[0xdf];
	unsigned short configuration_register;
	unsigned short pin_replacement_register;
	unsigned short socket_and_copy_register;

};


/* timeout for transmit watchdog timer, AP default is 8 sec */
#define AWC_TX_TIMEOUT			(HZ * 8) 



/***************************  REGISTER OFFSETS *********************/
#define awc_Command_register 		0x00
#define awc_Param0_register 		0x02
#define awc_Param1_register 		0x04
#define awc_Param2_register 		0x06
#define awc_Status_register 		0x08
#define awc_Resp0_register 		0x0A
#define awc_Resp1_register 		0x0C
#define awc_Resp2_register 		0x0E
#define awc_EvStat_register 		0x30
#define awc_EvIntEn_register 		0x32
#define awc_EvAck_register 		0x34
#define awc_SWSupport0_register 	0x28
#define awc_SWSupport1_register 	0x2A
#define awc_SWSupport2_register 	0x2C
#define awc_SWSupport3_register 	0x2E
#define awc_LinkStatus_register 	0x10
// Memory access  RID FID
#define awc_Select0_register 		0x18
#define awc_Offset0_register 		0x1C
#define awc_Data0_register 		0x36
#define awc_Select1_register 		0x1A
#define awc_Offset1_register 		0x1E
#define awc_Data1_register 		0x38
//
#define awc_RxFID_register 		0x20
#define awc_TxAllocFID_register 	0x22
#define awc_TxComplFID_register 	0x24
#define awc_AuxPage_register 		0x3A
#define awc_AuxOffset_register 		0x3C
#define awc_AuxData_register 		0x3E


struct awc_bap {
	u16 select;
	u16 offset;
	u16 data;
	volatile int lock;
	volatile int	status;
	struct semaphore sem;
	my_spinlock_t spinlock;
	unsigned long flags;
};



#define AWC_COMMAND_STATE_WAIT_CMD_BUSY		1
#define AWC_COMMAND_STATE_WAIT_CMD_ACK		2
#define AWC_COMMAND_STATE_WAIT_BAP_BUSY		3
#define AWC_COMMAND_STATE_BAP_NOT_SET		4
#define AWC_COMMAND_STATE_BAP_SET		5

struct awc_command {
	volatile int		state;
	volatile int		lock_state;
	struct net_device *		dev;
	struct awc_private *	priv;
	u16			port;
	struct awc_bap * 	bap;
	u16			command;
	u16			par0;
	u16			par1;
	u16			par2;
	u16			status;
	u16			resp0;
	u16			resp1;
	u16			resp2;
	u16			rid;
	u16			offset;
	u16			len;
	void *			buff;

};




#define DOWN(a) down_interruptible( a ) ; 
//	if (in_interrupt()) { down_interruptible( a ) ; } else printk("semaphore DOWN in interrupt tried \n");
#define UP(a)   up( a ) ;
//	if (in_interrupt()) {up( a ) ; } else printk("semaphore UP in interrupt tried \n");

/*	if (!in_interrupt())\
	printk("bap lock under cli but not in int\n");\
*/

#define AWC_LOCK_COMMAND_ISSUING(a) my_spin_lock_irqsave(&a->command_issuing_spinlock,a->command_issuing_spinlock_flags);
#define AWC_UNLOCK_COMMAND_ISSUING(a) my_spin_unlock_irqrestore(&a->command_issuing_spinlock,a->command_issuing_spinlock_flags);

#define AWC_BAP_LOCK_UNDER_CLI_REAL(cmd) \
 	if (!cmd.priv) {\
		printk(KERN_CRIT "awc4500: no priv present in command !");\
	}\
	cmd.bap = &(cmd.priv->bap1);\
	if (both_bap_lock)\
	my_spin_lock_irqsave(&cmd.priv->both_bap_spinlock,cmd.priv->both_bap_spinlock_flags);\
	if (cmd.bap){\
		my_spin_lock_irqsave(&(cmd.bap->spinlock),cmd.bap->flags);\
		cmd.bap->lock++;\
		if (cmd.bap->lock > 1)\
			printk("Bap 1 lock high\n");\
		cmd.lock_state |= AWC_BAP_LOCKED;\
	}

#define AWC_BAP_LOCK_NOT_CLI_REAL(cmd) {\
	if (in_interrupt())\
	printk("bap lock not cli in int\n");\
 	if (!cmd.priv) {\
		printk(KERN_CRIT "awc4500: no priv present in command,lockup follows !");\
	}\
	cmd.bap = &(cmd.priv->bap0);\
	if (both_bap_lock)\
		my_spin_lock_irqsave(&cmd.priv->both_bap_spinlock,cmd.priv->both_bap_spinlock_flags);\
	my_spin_lock_irqsave(&(cmd.bap->spinlock),cmd.bap->flags);\
	DOWN(&(cmd.priv->bap0.sem));\
	cmd.bap->lock++;\
	if (cmd.bap->lock > 1)\
		printk("Bap 0 lock high\n");\
	cmd.lock_state |= AWC_BAP_SEMALOCKED;\
}

#define AWC_BAP_LOCK_NOT_CLI_CLI_REAL(cmd) {\
	cmd.bap = &(cmd.priv->bap0);\
	if (both_bap_lock)\
		my_spin_lock_irqsave(&cmd.priv->both_bap_spinlock,cmd.priv->both_bap_spinlock_flags);\
	my_spin_lock_irqsave(&(cmd.bap->spinlock),cmd.bap->flags);\
	cmd.bap->lock++;\
	if (cmd.bap->lock > 1)\
		printk("Bap 0 lock high\n");\
	cmd.lock_state |= AWC_BAP_LOCKED;\
}

#define BAP_LOCK_ANY(cmd)\
	if (in_interrupt())	AWC_BAP_LOCK_NOT_CLI_CLI_REAL(cmd)\
	else AWC_BAP_LOCK_NOT_CLI_REAL(cmd)
	
#define AWC_BAP_LOCK_NOT_CLI(cmd)	BAP_LOCK_ANY(cmd)
#define AWC_BAP_LOCK_UNDER_CLI(cmd)	AWC_BAP_LOCK_UNDER_CLI_REAL(cmd)
/*
	if (!cmd.priv->bap1.lock ) {BAP_LOCK_ANY(cmd);}\
	else AWC_BAP_LOCK_NOT_CLI_CLI_REAL(cmd);
*/	
#define AWC_BAP_LOCKED 		0x01
#define AWC_BAP_SEMALOCKED 	0x02

#define AWC_BAP_BUSY	0x8000
#define AWC_BAP_ERR	0x4000
#define AWC_BAP_DONE	0x2000

#define AWC_CLI		1
#define AWC_NOT_CLI 	2

/*#define WAIT61x3	inb(0x61);\
         		inb(0x61);\
                    	inb(0x61);
*/ 
#define WAIT61x3 	udelay(bap_sleep)                  	

#define AWC_INIT_COMMAND(context, a_com, a_dev,a_cmmand,a_pr0, a_rid, a_offset, a_len, a_buff) {\
	memset(&a_com,0,sizeof(a_com) );\
	a_com.dev = a_dev;\
	a_com.priv = a_dev->priv;\
	a_com.port = a_dev->base_addr;\
	a_com.bap = NULL;\
	a_com.command = a_cmmand;\
	a_com.par0 = a_pr0;\
	a_com.rid = a_rid;\
	a_com.offset = a_offset;\
	a_com.len = a_len;\
	a_com.buff = a_buff;\
	a_com.lock_state = 0;\
};

/* v鋑a veider asi j鋜gnevast 
 makrost v鋖ja j鋏tud	if (cmd.bap) AWC_IN((cmd.bap)->data);\
*/

#define AWC_BAP_UNLOCK(com) { \
	if (com.bap){ \
		if ( (com.lock_state & AWC_BAP_SEMALOCKED) &&\
		     (com.lock_state & AWC_BAP_LOCKED) ){\
		     	printk("Both Sema and simple lock \n");\
		}\
		if ( com.lock_state & AWC_BAP_SEMALOCKED ){\
			 com.bap->lock--; \
			 com.lock_state &= ~AWC_BAP_SEMALOCKED;\
			 UP(&(com.bap->sem)); \
			 my_spin_unlock_irqrestore(&(cmd.bap->spinlock),cmd.bap->flags);\
		} else if (com.lock_state & AWC_BAP_LOCKED){\
			 com.bap->lock--; \
			 com.lock_state &= ~AWC_BAP_LOCKED;\
			 my_spin_unlock_irqrestore(&(cmd.bap->spinlock),cmd.bap->flags);\
		}\
	}\
	if (both_bap_lock)\
		my_spin_unlock_irqrestore(&cmd.priv->both_bap_spinlock,cmd.priv->both_bap_spinlock_flags);\
}

#define AWC_RELEASE_COMMAND(com) {\
		AWC_BAP_UNLOCK(cmd);\
	}



#define awc_manufacturer_code 	0x015F
#define awc_product_code	0x0005


#define awc_write(base,register,u16value) outw(u16value, (base)+(register))
#define awc_read(base,register)           inw((base)+(register))
#define AWC_OUT(base,val)		outw(val, base)
#define AWC_IN(base)			inw(base)


#define awc_read_response(cmd)	{	\
	cmd->status=awc_read(cmd->port,awc_Status_register);\
	cmd->resp0=awc_read(cmd->port,awc_Resp0_register);\
	cmd->resp1=awc_read(cmd->port,awc_Resp1_register);\
	cmd->resp2=awc_read(cmd->port,awc_Resp2_register);\
};

#define awc_command_busy(base)		(awc_read(base,awc_Command_register) & 0x8000)
#define awc_command_read(base)		awc_read(base,awc_Command_register)
#define awc_command_write(base,cmd)	awc_write(base,awc_Command_register,cmd) 
#define awc_event_status_Awake(base)	(awc_read(base,awc_EvStat_register) & 0x0100)
#define awc_event_status_Link(base)	(awc_read(base,awc_EvStat_register) & 0x0080)
#define awc_event_status_Cmd(base)	(awc_read(base,awc_EvStat_register) & 0x0010)
#define awc_event_status_Alloc(base)	(awc_read(base,awc_EvStat_register) & 0x0008)
#define awc_event_status_TxExc(base)	(awc_read(base,awc_EvStat_register) & 0x0004)
#define awc_event_status_Tx(base)	(awc_read(base,awc_EvStat_register) & 0x0002)
#define awc_event_status_TxResp(base)	(awc_read(base,awc_EvStat_register) & 0x0006)
#define awc_event_status_Rx(base)	(awc_read(base,awc_EvStat_register) & 0x0001)
#define awc_event_status(base)		(awc_read(base,awc_EvStat_register))

#define awc_Link_Status(base)		awc_read(base,awc_LinkStatus_register)

#define awc_Rx_Fid(base)		awc_read(base,awc_RxFID_register)
#define awc_Tx_Allocated_Fid(base)	awc_read(base,awc_TxAllocFID_register)
#define awc_Tx_Compl_Fid(base)		awc_read(base,awc_TxComplFID_register)

#define awc_event_ack_ClrStckCmdBsy(base) awc_write(base,awc_EvAck_register, 0x4000)
#define awc_event_ack_WakeUp(base)	awc_write(base,awc_EvAck_register, 0x2000)
#define awc_event_ack_Awaken(base)	awc_write(base,awc_EvAck_register, 0x0100)
#define awc_event_ack_Link(base)	awc_write(base,awc_EvAck_register, 0x0080)
#define awc_event_ack_Cmd(base)		awc_write(base,awc_EvAck_register, 0x0010)
#define awc_event_ack_Alloc(base)	awc_write(base,awc_EvAck_register, 0x0008)
#define awc_event_ack_TxExc(base)	awc_write(base,awc_EvAck_register, 0x0004)
#define awc_event_ack_Tx(base)		awc_write(base,awc_EvAck_register, 0x0002)
#define awc_event_ack_Rx(base)		awc_write(base,awc_EvAck_register, 0x0001)

#define awc_event_ack(base,ints)	awc_write(base,awc_EvAck_register,ints)

#define awc_ints_enabled(base)		(awc_read(base,awc_EvIntEn_register))
#define awc_ints_enable(base,ints)	awc_write(base,awc_EvIntEn_register,ints)



/************************  	RX TX 	BUFF	************************/


struct aironet4500_radio_rx_header {
	u32	RxTime;
	u16	Status;
	u16	PayloadLength;
	u8	Reserved0;
	u8	RSSI;
	u8	Rate;
	u8	Frequency;
	u8	Rx_association_count;
	u8 	Reserved1[3];
	u8	PLCP_header[4];

};


struct aironet4500_radio_tx_header {
	u32	SWSupport;
	u16	Status;
	#define aironet4500_tx_status_max_retries	0x0002
	#define aironet4500_tx_status_lifetime_exceeded	0x0004
	#define aironet4500_tx_status_AID_failure	0x0008
	#define aironet4500_tx_status_MAC_disabled	0x0010
	#define aironet4500_tx_status_association_lost	0x0020
	u16	PayloadLength;
	u16	TX_Control;
	#define aironet4500_tx_control_tx_ok_event_enable 	0x0002
	#define aironet4500_tx_control_tx_fail_event_enable 	0x0004
	#define aironet4500_tx_control_header_type_802_11 	0x0008
	#define aironet4500_tx_control_payload_type_llc 	0x0010
	#define aironet4500_tx_control_no_release 		0x0020
	#define aironet4500_tx_control_reuse_fid \
		(aironet4500_tx_control_tx_ok_event_enable |\
		 aironet4500_tx_control_tx_fail_event_enable |\
		  aironet4500_tx_control_no_release)
	#define aironet4500_tx_control_no_retries 		0x0040
	#define aironet4500_tx_control_clear_AID 		0x0080
	#define aironet4500_tx_control_strict_order 		0x0100
	#define aironet4500_tx_control_use_rts 			0x0200
	u16	AID;
	u8	Tx_Long_Retry;
	u8	Tx_Short_Retry;
	u8	tx_association_count;
	u8	tx_bit_rate;
	#define	aironet4500_tx_bit_rate_automatic 0
	#define aironet4500_tx_bit_rate_500kbps	1
	#define aironet4500_tx_bit_rate_1Mbps	2
	#define aironet4500_tx_bit_rate_2Mbps	4
	u8	Max_Long_Retry;
	u8	Max_Short_Retry;
	u8	Reserved0[2];
};


struct aironet4500_rx_fid {

	u16						rid;
	struct aironet4500_radio_rx_header 		radio_rx;
	struct ieee_802_11_header 	   		ieee_802_11;
	u16 						gap_length;
	struct ieee_802_3_header	   		ieee_802_3;
	u8					*	payload;
};


struct aironet4500_tx_fid {

	u16						fid;
	u16						fid_size;
	struct aironet4500_radio_tx_header 		radio_tx;
	struct ieee_802_11_header 	   		ieee_802_11;
	u16 						gap_length;