📄 tbconvrt.c
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/* power management profile to OSPM. It doesn't have any*/ /* 0.71 equivalence. Since we don't know what kind of */ /* 64-bit system this is, we will pick unspecified. */ FADT2->prefer_PM_profile = PM_UNSPECIFIED; /* Port address of SMI command port */ /* We shouldn't use this port because IA64 doesn't */ /* have or use SMI. It has PMI. */ FADT2->smi_cmd = (u32)(FADT71->smi_cmd & 0xFFFFFFFF); /* processor performance state control*/ /* The value OSPM writes to the SMI_CMD register to assume */ /* processor performance state control responsibility. */ /* There isn't any equivalence in 0.71 */ /* Again this should be meaningless for IA64 */ /* FADT2->Pstate_cnt = 0; */ /* The 32-bit Power management and GPE registers are */ /* not valid in IA-64 and we are not going to use them */ /* so leaving them pre-zeroed. */ /* Support for the _CST object and C States change notification.*/ /* This data item hasn't any 0.71 equivalence so leaving it zero.*/ /* FADT2->Cst_cnt = 0; */ /* number of flush strides that need to be read */ /* No 0.71 equivalence. Leave pre-zeroed. */ /* FADT2->Flush_size = 0; */ /* Processor's memory cache line width, in bytes */ /* No 0.71 equivalence. Leave pre-zeroed. */ /* FADT2->Flush_stride = 0; */ /* Processor抯 duty cycle index in processor's P_CNT reg*/ /* No 0.71 equivalence. Leave pre-zeroed. */ /* FADT2->Duty_offset = 0; */ /* Processor抯 duty cycle value bit width in P_CNT register.*/ /* No 0.71 equivalence. Leave pre-zeroed. */ /* FADT2->Duty_width = 0; */ /* Since there isn't any equivalence in 0.71 */ /* and since Big_sur had to support legacy */ FADT2->iapc_boot_arch = BAF_LEGACY_DEVICES; /* Copy to ACPI 2.0 64-BIT Extended Addresses */ FADT2->Xfirmware_ctrl = FADT71->firmware_ctrl; FADT2->Xdsdt = FADT71->dsdt; /* Extract the address space IDs */ pm1_address_space = (u8)((FADT71->address_space & PM1_BLK_ADDRESS_SPACE) >> 1); pm2_address_space = (u8)((FADT71->address_space & PM2_CNT_BLK_ADDRESS_SPACE) >> 2); pm_timer_address_space = (u8)((FADT71->address_space & PM_TMR_BLK_ADDRESS_SPACE) >> 3); gpe0address_space = (u8)((FADT71->address_space & GPE0_BLK_ADDRESS_SPACE) >> 4); gpe1_address_space = (u8)((FADT71->address_space & GPE1_BLK_ADDRESS_SPACE) >> 5); /* * Convert the 0.71 (non-GAS style) Block addresses to V2.0 GAS structures, * in this order: * * PM 1_a Events * PM 1_b Events * PM 1_a Control * PM 1_b Control * PM 2 Control * PM Timer Control * GPE Block 0 * GPE Block 1 */ ASL_BUILD_GAS_FROM_ENTRY (FADT2->Xpm1a_evt_blk, FADT71->pm1_evt_len, FADT71->pm1a_evt_blk, pm1_address_space); ASL_BUILD_GAS_FROM_ENTRY (FADT2->Xpm1b_evt_blk, FADT71->pm1_evt_len, FADT71->pm1b_evt_blk, pm1_address_space); ASL_BUILD_GAS_FROM_ENTRY (FADT2->Xpm1a_cnt_blk, FADT71->pm1_cnt_len, FADT71->pm1a_cnt_blk, pm1_address_space); ASL_BUILD_GAS_FROM_ENTRY (FADT2->Xpm1b_cnt_blk, FADT71->pm1_cnt_len, FADT71->pm1b_cnt_blk, pm1_address_space); ASL_BUILD_GAS_FROM_ENTRY (FADT2->Xpm2_cnt_blk, FADT71->pm2_cnt_len, FADT71->pm2_cnt_blk, pm2_address_space); ASL_BUILD_GAS_FROM_ENTRY (FADT2->Xpm_tmr_blk, FADT71->pm_tm_len, FADT71->pm_tmr_blk, pm_timer_address_space); ASL_BUILD_GAS_FROM_ENTRY (FADT2->Xgpe0blk, FADT71->gpe0blk_len, FADT71->gpe0blk, gpe0address_space); ASL_BUILD_GAS_FROM_ENTRY (FADT2->Xgpe1_blk, FADT71->gpe1_blk_len, FADT71->gpe1_blk, gpe1_address_space);#else /* ACPI 1.0 FACS */ /* The BIOS stored FADT should agree with Revision 1.0 */ FADT1 = (FADT_DESCRIPTOR_REV1*) acpi_gbl_FADT; /* * Copy the table header and the common part of the tables * The 2.0 table is an extension of the 1.0 table, so the * entire 1.0 table can be copied first, then expand some * fields to 64 bits. */ MEMCPY (FADT2, FADT1, sizeof (FADT_DESCRIPTOR_REV1)); /* Convert table pointers to 64-bit fields */ FADT2->Xfirmware_ctrl = (UINT64) FADT1->firmware_ctrl; FADT2->Xdsdt = (UINT64) FADT1->dsdt; /* System Interrupt Model isn't used in ACPI 2.0*/ /* FADT2->Reserved1 = 0; */ /* This field is set by the OEM to convey the preferred */ /* power management profile to OSPM. It doesn't have any*/ /* 1.0 equivalence. Since we don't know what kind of */ /* 32-bit system this is, we will pick unspecified. */ FADT2->prefer_PM_profile = PM_UNSPECIFIED; /* Processor Performance State Control. This is the value */ /* OSPM writes to the SMI_CMD register to assume processor */ /* performance state control responsibility. There isn't */ /* any equivalence in 1.0. So leave it zeroed. */ FADT2->pstate_cnt = 0; /* Support for the _CST object and C States change notification.*/ /* This data item hasn't any 1.0 equivalence so leaving it zero.*/ FADT2->cst_cnt = 0; /* Since there isn't any equivalence in 1.0 and since it */ /* is highly likely that a 1.0 system has legacy support. */ FADT2->iapc_boot_arch = BAF_LEGACY_DEVICES; /* * Convert the V1.0 Block addresses to V2.0 GAS structures * in this order: * * PM 1_a Events * PM 1_b Events * PM 1_a Control * PM 1_b Control * PM 2 Control * PM Timer Control * GPE Block 0 * GPE Block 1 */ ASL_BUILD_GAS_FROM_V1_ENTRY (FADT2->Xpm1a_evt_blk, FADT1->pm1_evt_len, FADT1->pm1a_evt_blk); ASL_BUILD_GAS_FROM_V1_ENTRY (FADT2->Xpm1b_evt_blk, FADT1->pm1_evt_len, FADT1->pm1b_evt_blk); ASL_BUILD_GAS_FROM_V1_ENTRY (FADT2->Xpm1a_cnt_blk, FADT1->pm1_cnt_len, FADT1->pm1a_cnt_blk); ASL_BUILD_GAS_FROM_V1_ENTRY (FADT2->Xpm1b_cnt_blk, FADT1->pm1_cnt_len, FADT1->pm1b_cnt_blk); ASL_BUILD_GAS_FROM_V1_ENTRY (FADT2->Xpm2_cnt_blk, FADT1->pm2_cnt_len, FADT1->pm2_cnt_blk); ASL_BUILD_GAS_FROM_V1_ENTRY (FADT2->Xpm_tmr_blk, FADT1->pm_tm_len, FADT1->pm_tmr_blk); ASL_BUILD_GAS_FROM_V1_ENTRY (FADT2->Xgpe0blk, FADT1->gpe0blk_len, FADT1->gpe0blk); ASL_BUILD_GAS_FROM_V1_ENTRY (FADT2->Xgpe1_blk, FADT1->gpe1_blk_len, FADT1->gpe1_blk);#endif } /* * Global FADT pointer will point to the common V2.0 FADT */ acpi_gbl_FADT = FADT2; /* Free the original table */ table_desc = &acpi_gbl_acpi_tables[ACPI_TABLE_FADT]; acpi_tb_delete_single_table (table_desc); /* Install the new table */ table_desc->pointer = (ACPI_TABLE_HEADER *) acpi_gbl_FADT; table_desc->base_pointer = acpi_gbl_FADT; table_desc->allocation = ACPI_MEM_ALLOCATED; table_desc->length = sizeof (FADT_DESCRIPTOR_REV2); /* Dump the FADT Header */ /* Dump the entire FADT */ return (AE_OK);}/******************************************************************************* * * FUNCTION: Acpi_tb_convert_table_facs * * PARAMETERS: * * RETURN: * * DESCRIPTION: * ******************************************************************************/ACPI_STATUSacpi_tb_build_common_facs ( ACPI_TABLE_DESC *table_info){ ACPI_COMMON_FACS *common_facs;#ifdef _IA64 FACS_DESCRIPTOR_REV071 *FACS71;#else FACS_DESCRIPTOR_REV1 *FACS1;#endif FACS_DESCRIPTOR_REV2 *FACS2; /* Allocate a common FACS */ common_facs = acpi_cm_callocate (sizeof (ACPI_COMMON_FACS)); if (!common_facs) { return (AE_NO_MEMORY); } /* Copy fields to the new FACS */ if (acpi_gbl_RSDP->revision < 2) {#ifdef _IA64 /* 0.71 FACS */ FACS71 = (FACS_DESCRIPTOR_REV071 *) acpi_gbl_FACS; common_facs->global_lock = (u32 *) &(FACS71->global_lock); common_facs->firmware_waking_vector = &FACS71->firmware_waking_vector; common_facs->vector_width = 64;#else /* ACPI 1.0 FACS */ FACS1 = (FACS_DESCRIPTOR_REV1 *) acpi_gbl_FACS; common_facs->global_lock = &(FACS1->global_lock); common_facs->firmware_waking_vector = (UINT64 *) &FACS1->firmware_waking_vector; common_facs->vector_width = 32;#endif } else { /* ACPI 2.0 FACS */ FACS2 = (FACS_DESCRIPTOR_REV2 *) acpi_gbl_FACS; common_facs->global_lock = &(FACS2->global_lock); common_facs->firmware_waking_vector = &FACS2->Xfirmware_waking_vector; common_facs->vector_width = 64; } /* Set the global FACS pointer to point to the common FACS */ acpi_gbl_FACS = common_facs; return (AE_OK);}
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