iphase.c

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  srv_p->rdf        = 0xb;
  srv_p->nrm        = 0x4;
  srv_p->trm        = 0x7;
  srv_p->cdf        = 0x3;
  srv_p->adtf       = 50;
}

static int
ia_open_abr_vc(IADEV *dev, srv_cls_param_t *srv_p, 
                                                struct atm_vcc *vcc, u8 flag)
{
  f_vc_abr_entry  *f_abr_vc;
  r_vc_abr_entry  *r_abr_vc;
  u32		icr;
  u8		trm, nrm, crm;
  u16		adtf, air, *ptr16;	
  f_abr_vc =(f_vc_abr_entry *)dev->MAIN_VC_TABLE_ADDR;
  f_abr_vc += vcc->vci;       
  switch (flag) {
     case 1: /* FFRED initialization */
#if 0  /* sanity check */
       if (srv_p->pcr == 0)
          return INVALID_PCR;
       if (srv_p->pcr > dev->LineRate)
          srv_p->pcr = dev->LineRate;
       if ((srv_p->mcr + dev->sum_mcr) > dev->LineRate)
	  return MCR_UNAVAILABLE;
       if (srv_p->mcr > srv_p->pcr)
	  return INVALID_MCR;
       if (!(srv_p->icr))
	  srv_p->icr = srv_p->pcr;
       if ((srv_p->icr < srv_p->mcr) || (srv_p->icr > srv_p->pcr))
	  return INVALID_ICR;
       if ((srv_p->tbe < MIN_TBE) || (srv_p->tbe > MAX_TBE))
	  return INVALID_TBE;
       if ((srv_p->frtt < MIN_FRTT) || (srv_p->frtt > MAX_FRTT))
	  return INVALID_FRTT;
       if (srv_p->nrm > MAX_NRM)
	  return INVALID_NRM;
       if (srv_p->trm > MAX_TRM)
	  return INVALID_TRM;
       if (srv_p->adtf > MAX_ADTF)
          return INVALID_ADTF;
       else if (srv_p->adtf == 0)
	  srv_p->adtf = 1;
       if (srv_p->cdf > MAX_CDF)
	  return INVALID_CDF;
       if (srv_p->rif > MAX_RIF)
	  return INVALID_RIF;
       if (srv_p->rdf > MAX_RDF)
	  return INVALID_RDF;
#endif
       memset ((caddr_t)f_abr_vc, 0, sizeof(f_vc_abr_entry));
       f_abr_vc->f_vc_type = ABR;
       nrm = 2 << srv_p->nrm;     /* (2 ** (srv_p->nrm +1)) */
			          /* i.e 2**n = 2 << (n-1) */
       f_abr_vc->f_nrm = nrm << 8 | nrm;
       trm = 100000/(2 << (16 - srv_p->trm));
       if ( trm == 0) trm = 1;
       f_abr_vc->f_nrmexp =(((srv_p->nrm +1) & 0x0f) << 12)|(MRM << 8) | trm;
       crm = srv_p->tbe / nrm;
       if (crm == 0) crm = 1;
       f_abr_vc->f_crm = crm & 0xff;
       f_abr_vc->f_pcr = cellrate_to_float(srv_p->pcr);
       icr = MIN( srv_p->icr, (srv_p->tbe > srv_p->frtt) ?
				((srv_p->tbe/srv_p->frtt)*1000000) :
				(1000000/(srv_p->frtt/srv_p->tbe)));
       f_abr_vc->f_icr = cellrate_to_float(icr);
       adtf = (10000 * srv_p->adtf)/8192;
       if (adtf == 0) adtf = 1; 
       f_abr_vc->f_cdf = ((7 - srv_p->cdf) << 12 | adtf) & 0xfff;
       f_abr_vc->f_mcr = cellrate_to_float(srv_p->mcr);
       f_abr_vc->f_acr = f_abr_vc->f_icr;
       f_abr_vc->f_status = 0x0042;
       break;
    case 0: /* RFRED initialization */	
       ptr16 = (u_short *)(dev->reass_ram + REASS_TABLE*dev->memSize); 
       *(ptr16 + vcc->vci) = NO_AAL5_PKT | REASS_ABR;
       r_abr_vc = (r_vc_abr_entry*)(dev->reass_ram+ABR_VC_TABLE*dev->memSize);
       r_abr_vc += vcc->vci;
       r_abr_vc->r_status_rdf = (15 - srv_p->rdf) & 0x000f;
       air = srv_p->pcr << (15 - srv_p->rif);
       if (air == 0) air = 1;
       r_abr_vc->r_air = cellrate_to_float(air);
       dev->testTable[vcc->vci]->vc_status = VC_ACTIVE | VC_ABR;
       dev->sum_mcr	   += srv_p->mcr;
       dev->n_abr++;
       break;
    default:
       break;
  }
  return	0;
}
static int ia_cbr_setup (IADEV *dev, struct atm_vcc *vcc) {
   u32 rateLow=0, rateHigh, rate;
   int entries;
   struct ia_vcc *ia_vcc;

   int   idealSlot =0, testSlot, toBeAssigned, inc;
   u32   spacing;
   u16  *SchedTbl, *TstSchedTbl;
   u16  cbrVC, vcIndex;
   u32   fracSlot    = 0;
   u32   sp_mod      = 0;
   u32   sp_mod2     = 0;

   /* IpAdjustTrafficParams */
   if (vcc->qos.txtp.max_pcr <= 0) {
      IF_ERR(printk("PCR for CBR not defined\n");)
      return -1;
   }
   rate = vcc->qos.txtp.max_pcr;
   entries = rate / dev->Granularity;
   IF_CBR(printk("CBR: CBR entries=0x%x for rate=0x%x & Gran=0x%x\n",
                                entries, rate, dev->Granularity);)
   if (entries < 1)
      IF_CBR(printk("CBR: Bandwidth smaller than granularity of CBR table\n");) 
   rateLow  =  entries * dev->Granularity;
   rateHigh = (entries + 1) * dev->Granularity;
   if (3*(rate - rateLow) > (rateHigh - rate))
      entries++;
   if (entries > dev->CbrRemEntries) {
      IF_CBR(printk("CBR: Not enough bandwidth to support this PCR.\n");)
      IF_CBR(printk("Entries = 0x%x, CbrRemEntries = 0x%x.\n",
                                       entries, dev->CbrRemEntries);)
      return -EBUSY;
   }   

   ia_vcc = INPH_IA_VCC(vcc);
   ia_vcc->NumCbrEntry = entries; 
   dev->sum_mcr += entries * dev->Granularity; 
   /* IaFFrednInsertCbrSched */
   // Starting at an arbitrary location, place the entries into the table
   // as smoothly as possible
   cbrVC   = 0;
   spacing = dev->CbrTotEntries / entries;
   sp_mod  = dev->CbrTotEntries % entries; // get modulo
   toBeAssigned = entries;
   fracSlot = 0;
   vcIndex  = vcc->vci;
   IF_CBR(printk("Vci=0x%x,Spacing=0x%x,Sp_mod=0x%x\n",vcIndex,spacing,sp_mod);)
   while (toBeAssigned)
   {
      // If this is the first time, start the table loading for this connection
      // as close to entryPoint as possible.
      if (toBeAssigned == entries)
      {
         idealSlot = dev->CbrEntryPt;
         dev->CbrEntryPt += 2;    // Adding 2 helps to prevent clumping
         if (dev->CbrEntryPt >= dev->CbrTotEntries) 
            dev->CbrEntryPt -= dev->CbrTotEntries;// Wrap if necessary
      } else {
         idealSlot += (u32)(spacing + fracSlot); // Point to the next location
         // in the table that would be  smoothest
         fracSlot = ((sp_mod + sp_mod2) / entries);  // get new integer part
         sp_mod2  = ((sp_mod + sp_mod2) % entries);  // calc new fractional part
      }
      if (idealSlot >= (int)dev->CbrTotEntries) 
         idealSlot -= dev->CbrTotEntries;  
      // Continuously check around this ideal value until a null
      // location is encountered.
      SchedTbl = (u16*)(dev->seg_ram+CBR_SCHED_TABLE*dev->memSize); 
      inc = 0;
      testSlot = idealSlot;
      TstSchedTbl = (u16*)(SchedTbl+testSlot);  //set index and read in value
      IF_CBR(printk("CBR Testslot 0x%x AT Location 0x%x, NumToAssign=%d\n",
                                testSlot, (u32)TstSchedTbl,toBeAssigned);) 
      memcpy((caddr_t)&cbrVC,(caddr_t)TstSchedTbl,sizeof(u16));
      while (cbrVC)  // If another VC at this location, we have to keep looking
      {
          inc++;
          testSlot = idealSlot - inc;
          if (testSlot < 0) { // Wrap if necessary
             testSlot += dev->CbrTotEntries;
             IF_CBR(printk("Testslot Wrap. STable Start=0x%x,Testslot=%d\n",
                                                       (u32)SchedTbl,testSlot);)
          }
          TstSchedTbl = (u16 *)(SchedTbl + testSlot);  // set table index
          memcpy((caddr_t)&cbrVC,(caddr_t)TstSchedTbl,sizeof(u16)); 
          if (!cbrVC)
             break;
          testSlot = idealSlot + inc;
          if (testSlot >= (int)dev->CbrTotEntries) { // Wrap if necessary
             testSlot -= dev->CbrTotEntries;
             IF_CBR(printk("TotCbrEntries=%d",dev->CbrTotEntries);)
             IF_CBR(printk(" Testslot=0x%x ToBeAssgned=%d\n", 
                                            testSlot, toBeAssigned);)
          } 
          // set table index and read in value
          TstSchedTbl = (u16*)(SchedTbl + testSlot);
          IF_CBR(printk("Reading CBR Tbl from 0x%x, CbrVal=0x%x Iteration %d\n",
                          (u32)TstSchedTbl,cbrVC,inc);) 
          memcpy((caddr_t)&cbrVC,(caddr_t)TstSchedTbl,sizeof(u16));
       } /* while */
       // Move this VCI number into this location of the CBR Sched table.
       memcpy((caddr_t)TstSchedTbl, (caddr_t)&vcIndex,sizeof(u16));
       dev->CbrRemEntries--;
       toBeAssigned--;
   } /* while */ 

   /* IaFFrednCbrEnable */
   dev->NumEnabledCBR++;
   if (dev->NumEnabledCBR == 1) {
       writew((CBR_EN | UBR_EN | ABR_EN | (0x23 << 2)), dev->seg_reg+STPARMS);
       IF_CBR(printk("CBR is enabled\n");)
   }
   return 0;
}
static void ia_cbrVc_close (struct atm_vcc *vcc) {
   IADEV *iadev;
   u16 *SchedTbl, NullVci = 0;
   u32 i, NumFound;

   iadev = INPH_IA_DEV(vcc->dev);
   iadev->NumEnabledCBR--;
   SchedTbl = (u16*)(iadev->seg_ram+CBR_SCHED_TABLE*iadev->memSize);
   if (iadev->NumEnabledCBR == 0) {
      writew((UBR_EN | ABR_EN | (0x23 << 2)), iadev->seg_reg+STPARMS);
      IF_CBR (printk("CBR support disabled\n");)
   }
   NumFound = 0;
   for (i=0; i < iadev->CbrTotEntries; i++)
   {
      if (*SchedTbl == vcc->vci) {
         iadev->CbrRemEntries++;
         *SchedTbl = NullVci;
         IF_CBR(NumFound++;)
      }
      SchedTbl++;   
   } 
   IF_CBR(printk("Exit ia_cbrVc_close, NumRemoved=%d\n",NumFound);)
}

static int ia_avail_descs(IADEV *iadev) {
   int tmp = 0;
   ia_hack_tcq(iadev);
   if (iadev->host_tcq_wr >= iadev->ffL.tcq_rd)
      tmp = (iadev->host_tcq_wr - iadev->ffL.tcq_rd) / 2;
   else
      tmp = (iadev->ffL.tcq_ed - iadev->ffL.tcq_rd + 2 + iadev->host_tcq_wr -
                   iadev->ffL.tcq_st) / 2;
   return tmp;
}    

static int ia_que_tx (IADEV *iadev) { 
   struct sk_buff *skb;
   int num_desc;
   struct atm_vcc *vcc;
   struct ia_vcc *iavcc;
   static int ia_pkt_tx (struct atm_vcc *vcc, struct sk_buff *skb);
   num_desc = ia_avail_descs(iadev);
   while (num_desc && (skb = skb_dequeue(&iadev->tx_backlog))) {
      if (!(vcc = ATM_SKB(skb)->vcc)) {
         dev_kfree_skb_any(skb);
         printk("ia_que_tx: Null vcc\n");
         break;
      }
      if (!test_bit(ATM_VF_READY,&vcc->flags)) {
         dev_kfree_skb_any(skb);
         printk("Free the SKB on closed vci %d \n", vcc->vci);
         break;
      }
      iavcc = INPH_IA_VCC(vcc);
      if (ia_pkt_tx (vcc, skb)) {
         skb_queue_head(&iadev->tx_backlog, skb);
      }
      num_desc--;
   }
   return 0;
}
void ia_tx_poll (IADEV *iadev) {
   struct atm_vcc *vcc = NULL;
   struct sk_buff *skb = NULL, *skb1 = NULL;
   struct ia_vcc *iavcc;
   IARTN_Q *  rtne;

   ia_hack_tcq(iadev);
   while ( (rtne = ia_deque_rtn_q(&iadev->tx_return_q))) {
       skb = rtne->data.txskb;
       if (!skb) {
           printk("ia_tx_poll: skb is null\n");
           return;
       }
       vcc = ATM_SKB(skb)->vcc;
       if (!vcc) {
           printk("ia_tx_poll: vcc is null\n");
           dev_kfree_skb_any(skb);
           return;
       }

       iavcc = INPH_IA_VCC(vcc);
       if (!iavcc) {
           printk("ia_tx_poll: iavcc is null\n");
           dev_kfree_skb_any(skb);
           return;
       }

       skb1 = skb_dequeue(&iavcc->txing_skb);
       while (skb1 && (skb1 != skb)) {
          if (!(IA_SKB_STATE(skb1) & IA_TX_DONE)) {
             printk("IA_tx_intr: Vci %d lost pkt!!!\n", vcc->vci);
          }
          IF_ERR(printk("Release the SKB not match\n");)
          if (vcc && (vcc->pop) && (skb1->len != 0))
          {
             vcc->pop(vcc, skb1);
             IF_EVENT(printk("Tansmit Done - skb 0x%lx return\n",
                                                          (long)skb1);)
          }
          else 
             dev_kfree_skb_any(skb1);
          skb1 = skb_dequeue(&iavcc->txing_skb);
       }                                                        
       if (!skb1) {
          IF_EVENT(printk("IA: Vci %d - skb not found requed\n",vcc->vci);)
          ia_enque_head_rtn_q (&iadev->tx_return_q, rtne);
          break;
       }
       if (vcc && (vcc->pop) && (skb->len != 0))
       {
          vcc->pop(vcc, skb);
          IF_EVENT(printk("Tx Done - skb 0x%lx return\n",(long)skb);)
       }
       else 
          dev_kfree_skb_any(skb);
       kfree(rtne);
    }
    ia_que_tx(iadev);
    return;
}
#if 0
static void ia_eeprom_put (IADEV *iadev, u32 addr, u_short val)
{
        u32	t;
	int	i;
	/*
	 * Issue a command to enable writes to the NOVRAM
	 */
	NVRAM_CMD (EXTEND + EWEN);
	NVRAM_CLR_CE;
	/*
	 * issue the write command
	 */
	NVRAM_CMD(IAWRITE + addr);
	/* 
	 * Send the data, starting with D15, then D14, and so on for 16 bits
	 */
	for (i=15; i>=0; i--) {
		NVRAM_CLKOUT (val & 0x8000);
		val <<= 1;
	}
	NVRAM_CLR_CE;
	CFG_OR(NVCE);
	t = readl(iadev->reg+IPHASE5575_EEPROM_ACCESS); 
	while (!(t & NVDO))
		t = readl(iadev->reg+IPHASE5575_EEPROM_ACCESS); 

	NVRAM_CLR_CE;
	/*
	 * disable writes again
	 */
	NVRAM_CMD(EXTEND + EWDS)
	NVRAM_CLR_CE;
	CFG_AND(~NVDI);
}
#endif

static u16 ia_eeprom_get (IADEV *iadev, u32 addr)
{
	u_short	val;
        u32	t;
	int	i;
	/*
	 * Read the first bit that was clocked with the falling edge of the
	 * the last command data clock
	 */