iphase.h

Linux内核源代码 为压缩文件 是<<Linux内核>>一书中的源代码

#define	MB25_IS_RCSE	0x02		/* Received Cell Symbol Error	     */
#define	MB25_IS_RFIFOO	0x01		/* Received FIFO Overrun	     */

/*
 * Diagnostic Control
 */
#define	MB25_DC_FTXCD	0x80		/* Force TxClav deassert	     */	
#define	MB25_DC_RXCOS	0x40		/* RxClav operation select	     */
#define	MB25_DC_ECEIO	0x20		/* Single/Multi-PHY config select    */
#define	MB25_DC_RLFLUSH	0x10		/* Clear receive FIFO		     */
#define	MB25_DC_IXPE	0x08		/* Insert xmit payload error	     */
#define	MB25_DC_IXHECE	0x04		/* Insert Xmit HEC Error	     */
#define	MB25_DC_LB_MASK	0x03		/* Loopback control mask	     */

#define	MB25_DC_LL	0x03		/* Line Loopback		     */
#define	MB25_DC_PL	0x02		/* PHY Loopback			     */
#define	MB25_DC_NM	0x00		

#define FE_MASK 	0x00F0
#define FE_MULTI_MODE	0x0000
#define FE_SINGLE_MODE  0x0010 
#define FE_UTP_OPTION  	0x0020
#define FE_25MBIT_PHY	0x0040
#define FE_DS3_PHY      0x0080          /* DS3 */
#define FE_E3_PHY       0x0090          /* E3 */
		     
extern void ia_mb25_init (IADEV *);

/*********************** SUNI_PM7345 PHY DEFINE HERE *********************/
typedef struct _suni_pm7345_t
{
    u_int suni_config;     /* SUNI Configuration */
    u_int suni_intr_enbl;  /* SUNI Interrupt Enable */
    u_int suni_intr_stat;  /* SUNI Interrupt Status */
    u_int suni_control;    /* SUNI Control */
    u_int suni_id_reset;   /* SUNI Reset and Identity */
    u_int suni_data_link_ctrl;
    u_int suni_rboc_conf_intr_enbl;
    u_int suni_rboc_stat;
    u_int suni_ds3_frm_cfg;
    u_int suni_ds3_frm_intr_enbl;
    u_int suni_ds3_frm_intr_stat;
    u_int suni_ds3_frm_stat;
    u_int suni_rfdl_cfg;
    u_int suni_rfdl_enbl_stat;
    u_int suni_rfdl_stat;
    u_int suni_rfdl_data;
    u_int suni_pmon_chng;
    u_int suni_pmon_intr_enbl_stat;
    u_int suni_reserved1[0x13-0x11];
    u_int suni_pmon_lcv_evt_cnt_lsb;
    u_int suni_pmon_lcv_evt_cnt_msb;
    u_int suni_pmon_fbe_evt_cnt_lsb;
    u_int suni_pmon_fbe_evt_cnt_msb;
    u_int suni_pmon_sez_det_cnt_lsb;
    u_int suni_pmon_sez_det_cnt_msb;
    u_int suni_pmon_pe_evt_cnt_lsb;
    u_int suni_pmon_pe_evt_cnt_msb;
    u_int suni_pmon_ppe_evt_cnt_lsb;
    u_int suni_pmon_ppe_evt_cnt_msb;
    u_int suni_pmon_febe_evt_cnt_lsb;
    u_int suni_pmon_febe_evt_cnt_msb;
    u_int suni_ds3_tran_cfg;
    u_int suni_ds3_tran_diag;
    u_int suni_reserved2[0x23-0x21];
    u_int suni_xfdl_cfg;
    u_int suni_xfdl_intr_st;
    u_int suni_xfdl_xmit_data;
    u_int suni_xboc_code;
    u_int suni_splr_cfg;
    u_int suni_splr_intr_en;
    u_int suni_splr_intr_st;
    u_int suni_splr_status;
    u_int suni_splt_cfg;
    u_int suni_splt_cntl;
    u_int suni_splt_diag_g1;
    u_int suni_splt_f1;
    u_int suni_cppm_loc_meters;
    u_int suni_cppm_chng_of_cppm_perf_meter;
    u_int suni_cppm_b1_err_cnt_lsb;
    u_int suni_cppm_b1_err_cnt_msb;
    u_int suni_cppm_framing_err_cnt_lsb;
    u_int suni_cppm_framing_err_cnt_msb;
    u_int suni_cppm_febe_cnt_lsb;
    u_int suni_cppm_febe_cnt_msb;
    u_int suni_cppm_hcs_err_cnt_lsb;
    u_int suni_cppm_hcs_err_cnt_msb;
    u_int suni_cppm_idle_un_cell_cnt_lsb;
    u_int suni_cppm_idle_un_cell_cnt_msb;
    u_int suni_cppm_rcv_cell_cnt_lsb;
    u_int suni_cppm_rcv_cell_cnt_msb;
    u_int suni_cppm_xmit_cell_cnt_lsb;
    u_int suni_cppm_xmit_cell_cnt_msb;
    u_int suni_rxcp_ctrl;
    u_int suni_rxcp_fctrl;
    u_int suni_rxcp_intr_en_sts;
    u_int suni_rxcp_idle_pat_h1;
    u_int suni_rxcp_idle_pat_h2;
    u_int suni_rxcp_idle_pat_h3;
    u_int suni_rxcp_idle_pat_h4;
    u_int suni_rxcp_idle_mask_h1;
    u_int suni_rxcp_idle_mask_h2;
    u_int suni_rxcp_idle_mask_h3;
    u_int suni_rxcp_idle_mask_h4;
    u_int suni_rxcp_cell_pat_h1;
    u_int suni_rxcp_cell_pat_h2;
    u_int suni_rxcp_cell_pat_h3;
    u_int suni_rxcp_cell_pat_h4;
    u_int suni_rxcp_cell_mask_h1;
    u_int suni_rxcp_cell_mask_h2;
    u_int suni_rxcp_cell_mask_h3;
    u_int suni_rxcp_cell_mask_h4;
    u_int suni_rxcp_hcs_cs;
    u_int suni_rxcp_lcd_cnt_threshold;
    u_int suni_reserved3[0x57-0x54];
    u_int suni_txcp_ctrl;
    u_int suni_txcp_intr_en_sts;
    u_int suni_txcp_idle_pat_h1;
    u_int suni_txcp_idle_pat_h2;
    u_int suni_txcp_idle_pat_h3;
    u_int suni_txcp_idle_pat_h4;
    u_int suni_txcp_idle_pat_h5;
    u_int suni_txcp_idle_payload;
    u_int suni_e3_frm_fram_options;
    u_int suni_e3_frm_maint_options;
    u_int suni_e3_frm_fram_intr_enbl;
    u_int suni_e3_frm_fram_intr_ind_stat;
    u_int suni_e3_frm_maint_intr_enbl;
    u_int suni_e3_frm_maint_intr_ind;
    u_int suni_e3_frm_maint_stat;
    u_int suni_reserved4;
    u_int suni_e3_tran_fram_options;
    u_int suni_e3_tran_stat_diag_options;
    u_int suni_e3_tran_bip_8_err_mask;
    u_int suni_e3_tran_maint_adapt_options;
    u_int suni_ttb_ctrl;
    u_int suni_ttb_trail_trace_id_stat;
    u_int suni_ttb_ind_addr;
    u_int suni_ttb_ind_data;
    u_int suni_ttb_exp_payload_type;
    u_int suni_ttb_payload_type_ctrl_stat;
    u_int suni_pad5[0x7f-0x71];
    u_int suni_master_test;
    u_int suni_pad6[0xff-0x80];
}suni_pm7345_t;

#define SUNI_PM7345_T suni_pm7345_t
#define SUNI_PM7345     0x20            /* Suni chip type */
#define SUNI_PM5346     0x30            /* Suni chip type */
/*
 * SUNI_PM7345 Configuration
 */
#define SUNI_PM7345_CLB         0x01    /* Cell loopback        */
#define SUNI_PM7345_PLB         0x02    /* Payload loopback     */
#define SUNI_PM7345_DLB         0x04    /* Diagnostic loopback  */
#define SUNI_PM7345_LLB         0x80    /* Line loopback        */
#define SUNI_PM7345_E3ENBL      0x40    /* E3 enable bit        */
#define SUNI_PM7345_LOOPT       0x10    /* LOOPT enable bit     */
#define SUNI_PM7345_FIFOBP      0x20    /* FIFO bypass          */
#define SUNI_PM7345_FRMRBP      0x08    /* Framer bypass        */
/*
 * DS3 FRMR Interrupt Enable
 */
#define SUNI_DS3_COFAE  0x80            /* Enable change of frame align */
#define SUNI_DS3_REDE   0x40            /* Enable DS3 RED state intr    */
#define SUNI_DS3_CBITE  0x20            /* Enable Appl ID channel intr  */
#define SUNI_DS3_FERFE  0x10            /* Enable Far End Receive Failure intr*/
#define SUNI_DS3_IDLE   0x08            /* Enable Idle signal intr      */
#define SUNI_DS3_AISE   0x04            /* Enable Alarm Indication signal intr*/
#define SUNI_DS3_OOFE   0x02            /* Enable Out of frame intr     */
#define SUNI_DS3_LOSE   0x01            /* Enable Loss of signal intr   */
 
/*
 * DS3 FRMR Status
 */
#define SUNI_DS3_ACE    0x80            /* Additional Configuration Reg */
#define SUNI_DS3_REDV   0x40            /* DS3 RED state                */
#define SUNI_DS3_CBITV  0x20            /* Application ID channel state */
#define SUNI_DS3_FERFV  0x10            /* Far End Receive Failure state*/
#define SUNI_DS3_IDLV   0x08            /* Idle signal state            */
#define SUNI_DS3_AISV   0x04            /* Alarm Indication signal state*/
#define SUNI_DS3_OOFV   0x02            /* Out of frame state           */
#define SUNI_DS3_LOSV   0x01            /* Loss of signal state         */

/*
 * E3 FRMR Interrupt/Status
 */
#define SUNI_E3_CZDI    0x40            /* Consecutive Zeros indicator  */
#define SUNI_E3_LOSI    0x20            /* Loss of signal intr status   */
#define SUNI_E3_LCVI    0x10            /* Line code violation intr     */
#define SUNI_E3_COFAI   0x08            /* Change of frame align intr   */
#define SUNI_E3_OOFI    0x04            /* Out of frame intr status     */
#define SUNI_E3_LOS     0x02            /* Loss of signal state         */
#define SUNI_E3_OOF     0x01            /* Out of frame state           */

/*
 * E3 FRMR Maintenance Status
 */
#define SUNI_E3_AISD    0x80            /* Alarm Indication signal state*/
#define SUNI_E3_FERF_RAI        0x40    /* FERF/RAI indicator           */
#define SUNI_E3_FEBE    0x20            /* Far End Block Error indicator*/

/*
 * RXCP Control/Status
 */
#define SUNI_DS3_HCSPASS        0x80    /* Pass cell with HEC errors    */
#define SUNI_DS3_HCSDQDB        0x40    /* Control octets in HCS calc   */
#define SUNI_DS3_HCSADD         0x20    /* Add coset poly               */
#define SUNI_DS3_HCK            0x10    /* Control FIFO data path integ chk*/
#define SUNI_DS3_BLOCK          0x08    /* Enable cell filtering        */
#define SUNI_DS3_DSCR           0x04    /* Disable payload descrambling */
#define SUNI_DS3_OOCDV          0x02    /* Cell delineation state       */
#define SUNI_DS3_FIFORST        0x01    /* Cell FIFO reset              */

/*
 * RXCP Interrupt Enable/Status
 */
#define SUNI_DS3_OOCDE  0x80            /* Intr enable, change in CDS   */
#define SUNI_DS3_HCSE   0x40            /* Intr enable, corr HCS errors */
#define SUNI_DS3_FIFOE  0x20            /* Intr enable, unco HCS errors */
#define SUNI_DS3_OOCDI  0x10            /* SYNC state                   */
#define SUNI_DS3_UHCSI  0x08            /* Uncorr. HCS errors detected  */
#define SUNI_DS3_COCAI  0x04            /* Corr. HCS errors detected    */
#define SUNI_DS3_FOVRI  0x02            /* FIFO overrun                 */
#define SUNI_DS3_FUDRI  0x01            /* FIFO underrun                */

extern void ia_suni_pm7345_init (IADEV *iadev);

///////////////////SUNI_PM7345 PHY DEFINE END /////////////////////////////

/* ia_eeprom define*/
#define MEM_SIZE_MASK   0x000F          /* mask of 4 bits defining memory size*/
#define MEM_SIZE_128K   0x0000          /* board has 128k buffer */
#define MEM_SIZE_512K   0x0001          /* board has 512K of buffer */
#define MEM_SIZE_1M     0x0002          /* board has 1M of buffer */
                                        /* 0x3 to 0xF are reserved for future */

#define FE_MASK         0x00F0          /* mask of 4 bits defining FE type */
#define FE_MULTI_MODE   0x0000          /* 155 MBit multimode fiber */
#define FE_SINGLE_MODE  0x0010          /* 155 MBit single mode laser */
#define FE_UTP_OPTION   0x0020          /* 155 MBit UTP front end */

#define	NOVRAM_SIZE	64
#define	CMD_LEN		10

/***********
 *
 *	Switches and defines for header files.
 *
 *	The following defines are used to turn on and off
 *	various options in the header files. Primarily useful
 *	for debugging.
 *
 ***********/

/*
 * a list of the commands that can be sent to the NOVRAM
 */

#define	EXTEND	0x100
#define	IAWRITE	0x140
#define	IAREAD	0x180
#define	ERASE	0x1c0

#define	EWDS	0x00
#define	WRAL	0x10
#define	ERAL	0x20
#define	EWEN	0x30

/*
 * these bits duplicate the hw_flip.h register settings
 * note: how the data in / out bits are defined in the flipper specification 
 */

#define	NVCE	0x02
#define	NVSK	0x01
#define	NVDO	0x08	
#define NVDI	0x04
/***********************
 *
 * This define ands the value and the current config register and puts
 * the result in the config register
 *
 ***********************/

#define	CFG_AND(val) { \
		u32 t; \
		t = readl(iadev->reg+IPHASE5575_EEPROM_ACCESS); \
		t &= (val); \
		writel(t, iadev->reg+IPHASE5575_EEPROM_ACCESS); \
	}

/***********************
 *
 * This define ors the value and the current config register and puts
 * the result in the config register
 *
 ***********************/

#define	CFG_OR(val) { \
		u32 t; \
		t =  readl(iadev->reg+IPHASE5575_EEPROM_ACCESS); \
		t |= (val); \
		writel(t, iadev->reg+IPHASE5575_EEPROM_ACCESS); \
	}

/***********************
 *
 * Send a command to the NOVRAM, the command is in cmd.
 *
 * clear CE and SK. Then assert CE.
 * Clock each of the command bits out in the correct order with SK
 * exit with CE still asserted
 *
 ***********************/

#define	NVRAM_CMD(cmd) { \
		int	i; \
		u_short c = cmd; \
		CFG_AND(~(NVCE|NVSK)); \
		CFG_OR(NVCE); \
		for (i=0; i<CMD_LEN; i++) { \
			NVRAM_CLKOUT((c & (1 << (CMD_LEN - 1))) ? 1 : 0); \
			c <<= 1; \
		} \
	}

/***********************
 *
 * clear the CE, this must be used after each command is complete
 *
 ***********************/

#define	NVRAM_CLR_CE	{CFG_AND(~NVCE)}

/***********************
 *
 * clock the data bit in bitval out to the NOVRAM.  The bitval must be
 * a 1 or 0, or the clockout operation is undefined
 *
 ***********************/

#define	NVRAM_CLKOUT(bitval) { \
		CFG_AND(~NVDI); \
		CFG_OR((bitval) ? NVDI : 0); \
		CFG_OR(NVSK); \
		CFG_AND( ~NVSK); \
	}

/***********************
 *
 * clock the data bit in and return a 1 or 0, depending on the value
 * that was received from the NOVRAM
 *
 ***********************/

#define	NVRAM_CLKIN(value) { \
		u32 _t; \
		CFG_OR(NVSK); \
		CFG_AND(~NVSK); \
		_t = readl(iadev->reg+IPHASE5575_EEPROM_ACCESS); \
		value = (_t & NVDO) ? 1 : 0; \
	}


#endif /* IPHASE_H */