📄 iphase.h
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rreg_t tmout_indx; /* index of pkt being tested for aging */ u_int filler1a[0x1c - 0x1a]; rreg_t vp_lkup_base; /* Base address for VP lookup table */ rreg_t vp_filter; /* VP filter register */ rreg_t abr_lkup_base; /* Base address of ABR VC Table */ u_int filler1f[0x24 - 0x1f]; rreg_t fdq_st_adr; /* Free desc queue start address */ rreg_t fdq_ed_adr; /* Free desc queue end address */ rreg_t fdq_rd_ptr; /* Free desc queue read pointer */ rreg_t fdq_wr_ptr; /* Free desc queue write pointer */ rreg_t pcq_st_adr; /* Packet Complete queue start address */ rreg_t pcq_ed_adr; /* Packet Complete queue end address */ rreg_t pcq_rd_ptr; /* Packet Complete queue read pointer */ rreg_t pcq_wr_ptr; /* Packet Complete queue write pointer */ rreg_t excp_st_adr; /* Exception queue start address */ rreg_t excp_ed_adr; /* Exception queue end address */ rreg_t excp_rd_ptr; /* Exception queue read pointer */ rreg_t excp_wr_ptr; /* Exception queue write pointer */ u_int filler30[0x34 - 0x30]; rreg_t raw_st_adr; /* Raw Cell start address */ rreg_t raw_ed_adr; /* Raw Cell end address */ rreg_t raw_rd_ptr; /* Raw Cell read pointer */ rreg_t raw_wr_ptr; /* Raw Cell write pointer */ rreg_t state_reg; /* State Register */ u_int filler39[0x42 - 0x39]; rreg_t buf_size; /* Buffer size */ u_int filler43; rreg_t xtra_rm_offset; /* Offset of the additional turnaround RM */ u_int filler45[0x84 - 0x45]; rreg_t drp_pkt_cntr_nc;/* Dropped Packet cntr, Not clear on rd */ rreg_t err_cntr_nc; /* Error Counter, Not clear on read */ u_int filler86[0x8c - 0x86]; rreg_t cell_ctr0_nc; /* Cell Counter 0, Not clear on read */ rreg_t cell_ctr1_nc; /* Cell Counter 1, Not clear on read */ u_int filler8e[0x100-0x8e]; /* pad out to full address space */} rfredn_t;typedef struct { /* Atlantic */ ffredn_t ffredn; /* F FRED */ rfredn_t rfredn; /* R FRED */} ia_regs_t;typedef struct { u_short f_vc_type; /* VC type */ u_short f_nrm; /* Nrm */ u_short f_nrmexp; /* Nrm Exp */ u_short reserved6; /* */ u_short f_crm; /* Crm */ u_short reserved10; /* Reserved */ u_short reserved12; /* Reserved */ u_short reserved14; /* Reserved */ u_short last_cell_slot; /* last_cell_slot_count */ u_short f_pcr; /* Peak Cell Rate */ u_short fraction; /* fraction */ u_short f_icr; /* Initial Cell Rate */ u_short f_cdf; /* */ u_short f_mcr; /* Minimum Cell Rate */ u_short f_acr; /* Allowed Cell Rate */ u_short f_status; /* */} f_vc_abr_entry;typedef struct { u_short r_status_rdf; /* status + RDF */ u_short r_air; /* AIR */ u_short reserved4[14]; /* Reserved */} r_vc_abr_entry; #define MRM 3#define MIN(x,y) ((x) < (y)) ? (x) : (y)typedef struct srv_cls_param { u32 class_type; /* CBR/VBR/ABR/UBR; use the enum above */ u32 pcr; /* Peak Cell Rate (24-bit) */ /* VBR parameters */ u32 scr; /* sustainable cell rate */ u32 max_burst_size; /* ?? cell rate or data rate */ /* ABR only UNI 4.0 Parameters */ u32 mcr; /* Min Cell Rate (24-bit) */ u32 icr; /* Initial Cell Rate (24-bit) */ u32 tbe; /* Transient Buffer Exposure (24-bit) */ u32 frtt; /* Fixed Round Trip Time (24-bit) */ #if 0 /* Additional Parameters of TM 4.0 */bits 31 30 29 28 27-25 24-22 21-19 18-9-----------------------------------------------------------------------------| NRM present | TRM prsnt | CDF prsnt | ADTF prsnt | NRM | TRM | CDF | ADTF |-----------------------------------------------------------------------------#endif /* 0 */ u8 nrm; /* Max # of Cells for each forward RM cell (3-bit) */ u8 trm; /* Time between forward RM cells (3-bit) */ u16 adtf; /* ACR Decrease Time Factor (10-bit) */ u8 cdf; /* Cutoff Decrease Factor (3-bit) */ u8 rif; /* Rate Increment Factor (4-bit) */ u8 rdf; /* Rate Decrease Factor (4-bit) */ u8 reserved; /* 8 bits to keep structure word aligned */} srv_cls_param_t;struct testTable_t { u16 lastTime; u16 fract; u8 vc_status;}; typedef struct { u16 vci; u16 error;} RX_ERROR_Q;typedef struct { u8 active: 1; u8 abr: 1; u8 ubr: 1; u8 cnt: 5;#define VC_ACTIVE 0x01#define VC_ABR 0x02#define VC_UBR 0x04} vcstatus_t; struct ia_rfL_t { u32 fdq_st; /* Free desc queue start address */ u32 fdq_ed; /* Free desc queue end address */ u32 fdq_rd; /* Free desc queue read pointer */ u32 fdq_wr; /* Free desc queue write pointer */ u32 pcq_st; /* Packet Complete queue start address */ u32 pcq_ed; /* Packet Complete queue end address */ u32 pcq_rd; /* Packet Complete queue read pointer */ u32 pcq_wr; /* Packet Complete queue write pointer */ };struct ia_ffL_t { u32 prq_st; /* Packet Ready Queue Start Address */ u32 prq_ed; /* Packet Ready Queue End Address */ u32 prq_wr; /* Packet Ready Queue write pointer */ u32 tcq_st; /* Transmit Complete Queue Start Address*/ u32 tcq_ed; /* Transmit Complete Queue End Address */ u32 tcq_rd; /* Transmit Complete Queue read pointer */};struct desc_tbl_t { u32 timestamp; struct ia_vcc *iavcc; struct sk_buff *txskb;}; typedef struct ia_rtn_q { struct desc_tbl_t data; struct ia_rtn_q *next, *tail;} IARTN_Q;#define SUNI_LOSV 0x04typedef struct { u32 suni_master_reset; /* SUNI Master Reset and Identity */ u32 suni_master_config; /* SUNI Master Configuration */ u32 suni_master_intr_stat; /* SUNI Master Interrupt Status */ u32 suni_reserved1; /* Reserved */ u32 suni_master_clk_monitor;/* SUNI Master Clock Monitor */ u32 suni_master_control; /* SUNI Master Clock Monitor */ u32 suni_reserved2[10]; /* Reserved */ u32 suni_rsop_control; /* RSOP Control/Interrupt Enable */ u32 suni_rsop_status; /* RSOP Status/Interrupt States */ u32 suni_rsop_section_bip8l;/* RSOP Section BIP-8 LSB */ u32 suni_rsop_section_bip8m;/* RSOP Section BIP-8 MSB */ u32 suni_tsop_control; /* TSOP Control */ u32 suni_tsop_diag; /* TSOP Disgnostics */ u32 suni_tsop_reserved[2]; /* TSOP Reserved */ u32 suni_rlop_cs; /* RLOP Control/Status */ u32 suni_rlop_intr; /* RLOP Interrupt Enable/Status */ u32 suni_rlop_line_bip24l; /* RLOP Line BIP-24 LSB */ u32 suni_rlop_line_bip24; /* RLOP Line BIP-24 */ u32 suni_rlop_line_bip24m; /* RLOP Line BIP-24 MSB */ u32 suni_rlop_line_febel; /* RLOP Line FEBE LSB */ u32 suni_rlop_line_febe; /* RLOP Line FEBE */ u32 suni_rlop_line_febem; /* RLOP Line FEBE MSB */ u32 suni_tlop_control; /* TLOP Control */ u32 suni_tlop_disg; /* TLOP Disgnostics */ u32 suni_tlop_reserved[14]; /* TLOP Reserved */ u32 suni_rpop_cs; /* RPOP Status/Control */ u32 suni_rpop_intr; /* RPOP Interrupt/Status */ u32 suni_rpop_reserved; /* RPOP Reserved */ u32 suni_rpop_intr_ena; /* RPOP Interrupt Enable */ u32 suni_rpop_reserved1[3]; /* RPOP Reserved */ u32 suni_rpop_path_sig; /* RPOP Path Signal Label */ u32 suni_rpop_bip8l; /* RPOP Path BIP-8 LSB */ u32 suni_rpop_bip8m; /* RPOP Path BIP-8 MSB */ u32 suni_rpop_febel; /* RPOP Path FEBE LSB */ u32 suni_rpop_febem; /* RPOP Path FEBE MSB */ u32 suni_rpop_reserved2[4]; /* RPOP Reserved */ u32 suni_tpop_cntrl_daig; /* TPOP Control/Disgnostics */ u32 suni_tpop_pointer_ctrl; /* TPOP Pointer Control */ u32 suni_tpop_sourcer_ctrl; /* TPOP Source Control */ u32 suni_tpop_reserved1[2]; /* TPOP Reserved */ u32 suni_tpop_arb_prtl; /* TPOP Arbitrary Pointer LSB */ u32 suni_tpop_arb_prtm; /* TPOP Arbitrary Pointer MSB */ u32 suni_tpop_reserved2; /* TPOP Reserved */ u32 suni_tpop_path_sig; /* TPOP Path Signal Lable */ u32 suni_tpop_path_status; /* TPOP Path Status */ u32 suni_tpop_reserved3[6]; /* TPOP Reserved */ u32 suni_racp_cs; /* RACP Control/Status */ u32 suni_racp_intr; /* RACP Interrupt Enable/Status */ u32 suni_racp_hdr_pattern; /* RACP Match Header Pattern */ u32 suni_racp_hdr_mask; /* RACP Match Header Mask */ u32 suni_racp_corr_hcs; /* RACP Correctable HCS Error Count */ u32 suni_racp_uncorr_hcs; /* RACP Uncorrectable HCS Error Count */ u32 suni_racp_reserved[10]; /* RACP Reserved */ u32 suni_tacp_control; /* TACP Control */ u32 suni_tacp_idle_hdr_pat; /* TACP Idle Cell Header Pattern */ u32 suni_tacp_idle_pay_pay; /* TACP Idle Cell Payld Octet Pattern */ u32 suni_tacp_reserved[5]; /* TACP Reserved */ u32 suni_reserved3[24]; /* Reserved */ u32 suni_master_test; /* SUNI Master Test */ u32 suni_reserved_test; /* SUNI Reserved for Test */} IA_SUNI;typedef struct _SUNI_STATS_{ u32 valid; // 1 = oc3 PHY card u32 carrier_detect; // GPIN input // RSOP: receive section overhead processor u16 rsop_oof_state; // 1 = out of frame u16 rsop_lof_state; // 1 = loss of frame u16 rsop_los_state; // 1 = loss of signal u32 rsop_los_count; // loss of signal count u32 rsop_bse_count; // section BIP-8 error count // RLOP: receive line overhead processor u16 rlop_ferf_state; // 1 = far end receive failure u16 rlop_lais_state; // 1 = line AIS u32 rlop_lbe_count; // BIP-24 count u32 rlop_febe_count; // FEBE count; // RPOP: receive path overhead processor u16 rpop_lop_state; // 1 = LOP u16 rpop_pais_state; // 1 = path AIS u16 rpop_pyel_state; // 1 = path yellow alert u32 rpop_bip_count; // path BIP-8 error count u32 rpop_febe_count; // path FEBE error count u16 rpop_psig; // path signal label value // RACP: receive ATM cell processor u16 racp_hp_state; // hunt/presync state u32 racp_fu_count; // FIFO underrun count u32 racp_fo_count; // FIFO overrun count u32 racp_chcs_count; // correctable HCS error count u32 racp_uchcs_count; // uncorrectable HCS error count} IA_SUNI_STATS; typedef struct iadev_t { /*-----base pointers into (i)chipSAR+ address space */ u32 *phy; /* base pointer into phy(SUNI) */ u32 *dma; /* base pointer into DMA control registers */ u32 *reg; /* base pointer to SAR registers - Bus Interface Control Regs */ u32 *seg_reg; /* base pointer to segmentation engine internal registers */ u32 *reass_reg; /* base pointer to reassemble engine internal registers */ u32 *ram; /* base pointer to SAR RAM */ unsigned int seg_ram; unsigned int reass_ram; struct dle_q tx_dle_q; struct free_desc_q *tx_free_desc_qhead; struct sk_buff_head tx_dma_q, tx_backlog; spinlock_t tx_lock; IARTN_Q tx_return_q; u32 close_pending;#if LINUX_VERSION_CODE >= 0x20303 wait_queue_head_t close_wait; wait_queue_head_t timeout_wait;#else struct wait_queue *close_wait; struct wait_queue *timeout_wait;#endif caddr_t *tx_buf; u16 num_tx_desc, tx_buf_sz, rate_limit; u32 tx_cell_cnt, tx_pkt_cnt; u32 MAIN_VC_TABLE_ADDR, EXT_VC_TABLE_ADDR, ABR_SCHED_TABLE_ADDR; struct dle_q rx_dle_q; struct free_desc_q *rx_free_desc_qhead; struct sk_buff_head rx_dma_q; spinlock_t rx_lock, misc_lock; struct atm_vcc **rx_open; /* list of all open VCs */ u16 num_rx_desc, rx_buf_sz, rxing; u32 rx_pkt_ram, rx_tmp_cnt, rx_tmp_jif; u32 RX_DESC_BASE_ADDR; u32 drop_rxpkt, drop_rxcell, rx_cell_cnt, rx_pkt_cnt; struct atm_dev *next_board; /* other iphase devices */ struct pci_dev *pci; int mem; unsigned long base_diff; /* virtual - real base address */ unsigned int real_base, base; /* real and virtual base address */ unsigned int pci_map_size; /*pci map size of board */ unsigned char irq; unsigned char bus; unsigned char dev_fn; u_short phy_type; u_short num_vc, memSize, memType; struct ia_ffL_t ffL; struct ia_rfL_t rfL; /* Suni stat */ // IA_SUNI_STATS suni_stats; unsigned char carrier_detect; /* CBR related */ // transmit DMA & Receive unsigned int tx_dma_cnt; // number of elements on dma queue unsigned int rx_dma_cnt; // number of elements on rx dma queue unsigned int NumEnabledCBR; // number of CBR VCI's enabled. CBR // receive MARK for Cell FIFO unsigned int rx_mark_cnt; // number of elements on mark queue unsigned int CbrTotEntries; // Total CBR Entries in Scheduling Table. unsigned int CbrRemEntries; // Remaining CBR Entries in Scheduling Table. unsigned int CbrEntryPt; // CBR Sched Table Entry Point. unsigned int Granularity; // CBR Granularity given Table Size. /* ABR related */ unsigned int sum_mcr, sum_cbr, LineRate; unsigned int n_abr; struct desc_tbl_t *desc_tbl; u_short host_tcq_wr; struct testTable_t **testTable;} IADEV; #define INPH_IA_DEV(d) ((IADEV *) (d)->dev_data) #define INPH_IA_VCC(v) ((struct ia_vcc *) (v)->dev_data) /******************* IDT77105 25MB/s PHY DEFINE *****************************/typedef struct { u_int mb25_master_ctrl; /* Master control */ u_int mb25_intr_status; /* Interrupt status */ u_int mb25_diag_control; /* Diagnostic control */ u_int mb25_led_hec; /* LED driver and HEC status/control */ u_int mb25_low_byte_counter; /* Low byte counter */ u_int mb25_high_byte_counter; /* High byte counter */} ia_mb25_t;/* * Master Control */#define MB25_MC_UPLO 0x80 /* UPLO */#define MB25_MC_DREC 0x40 /* Discard receive cell errors */#define MB25_MC_ECEIO 0x20 /* Enable Cell Error Interrupts Only */#define MB25_MC_TDPC 0x10 /* Transmit data parity check */#define MB25_MC_DRIC 0x08 /* Discard receive idle cells */#define MB25_MC_HALTTX 0x04 /* Halt Tx */#define MB25_MC_UMS 0x02 /* UTOPIA mode select */#define MB25_MC_ENABLED 0x01 /* Enable interrupt *//* * Interrupt Status */#define MB25_IS_GSB 0x40 /* GOOD Symbol Bit */ #define MB25_IS_HECECR 0x20 /* HEC error cell received */#define MB25_IS_SCR 0x10 /* "Short Cell" Received */#define MB25_IS_TPE 0x08 /* Trnamsit Parity Error */#define MB25_IS_RSCC 0x04 /* Receive Signal Condition change */⌨️ 快捷键说明
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