nicstar.h

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/******************************************************************************
 *
 * nicstar.h
 *
 * Header file for the nicstar device driver.
 *
 * Author: Rui Prior ([e-mail])
 * PowerPC support by Jay Talbott ([e-mail]) April 1999
 *
 * (C) INESC 1998
 *
 ******************************************************************************/


#ifndef _LINUX_NICSTAR_H_
#define _LINUX_NICSTAR_H_


/* Includes *******************************************************************/

#include <linux/types.h>
#include <linux/pci.h>
#include <linux/uio.h>
#include <linux/skbuff.h>
#include <linux/atmdev.h>
#include <linux/atm_nicstar.h>


/* Options ********************************************************************/

#undef NS_DEBUG_SPINLOCKS

#define NS_MAX_CARDS 4		/* Maximum number of NICStAR based cards
				   controlled by the device driver. Must
                                   be <= 5 */

#undef RCQ_SUPPORT		/* Do not define this for now */

#define NS_TST_NUM_ENTRIES 2340	/* + 1 for return */
#define NS_TST_RESERVED 340	/* N. entries reserved for UBR/ABR/VBR */

#define NS_SMBUFSIZE 48		/* 48, 96, 240 or 2048 */
#define NS_LGBUFSIZE 16384	/* 2048, 4096, 8192 or 16384 */
#define NS_RSQSIZE 8192		/* 2048, 4096 or 8192 */
#define NS_VPIBITS 2		/* 0, 1, 2, or 8 */

#define NS_MAX_RCTSIZE 4096	/* Number of entries. 4096 or 16384.
                                   Define 4096 only if (all) your card(s)
				   have 32K x 32bit SRAM, in which case
				   setting this to 16384 will just waste a
				   lot of memory.
				   Setting this to 4096 for a card with
				   128K x 32bit SRAM will limit the maximum
				   VCI. */

/*#define NS_PCI_LATENCY 64*/	/* Must be a multiple of 32 */

	/* Number of buffers initially allocated */
#define NUM_SB 32	/* Must be even */
#define NUM_LB 24	/* Must be even */
#define NUM_HB 8	/* Pre-allocated huge buffers */
#define NUM_IOVB 48	/* Iovec buffers */

	/* Lower level for count of buffers */
#define MIN_SB 8	/* Must be even */
#define MIN_LB 8	/* Must be even */
#define MIN_HB 6
#define MIN_IOVB 8

	/* Upper level for count of buffers */
#define MAX_SB 64	/* Must be even, <= 508 */
#define MAX_LB 48	/* Must be even, <= 508 */
#define MAX_HB 10
#define MAX_IOVB 80

	/* These are the absolute maximum allowed for the ioctl() */
#define TOP_SB 256	/* Must be even, <= 508 */
#define TOP_LB 128	/* Must be even, <= 508 */
#define TOP_HB 64
#define TOP_IOVB 256


#define MAX_TBD_PER_VC 1	/* Number of TBDs before a TSR */
#define MAX_TBD_PER_SCQ 10	/* Only meaningful for variable rate SCQs */

#undef ENABLE_TSQFIE

#define SCQFULL_TIMEOUT (5 * HZ)

#define NS_POLL_PERIOD (HZ)

#define PCR_TOLERANCE (1.0001)



/* ESI stuff ******************************************************************/

#define NICSTAR_EPROM_MAC_ADDR_OFFSET 0x6C


/* #defines *******************************************************************/

#define NS_IOREMAP_SIZE 4096

#define BUF_SM 0x00000000	/* These two are used for push_rxbufs() */
#define BUF_LG 0x00000001       /* CMD, Write_FreeBufQ, LBUF bit */

#define NS_HBUFSIZE 65568	/* Size of max. AAL5 PDU */
#define NS_MAX_IOVECS (2 + (65568 - NS_SMBUFSIZE) / \
                       (NS_LGBUFSIZE - (NS_LGBUFSIZE % 48)))
#define NS_IOVBUFSIZE (NS_MAX_IOVECS * (sizeof(struct iovec)))

#define NS_SMBUFSIZE_USABLE (NS_SMBUFSIZE - NS_SMBUFSIZE % 48)
#define NS_LGBUFSIZE_USABLE (NS_LGBUFSIZE - NS_LGBUFSIZE % 48)

#define NS_AAL0_HEADER (ATM_AAL0_SDU - ATM_CELL_PAYLOAD)	/* 4 bytes */

#define NS_SMSKBSIZE (NS_SMBUFSIZE + NS_AAL0_HEADER)
#define NS_LGSKBSIZE (NS_SMBUFSIZE + NS_LGBUFSIZE)


/* NICStAR structures located in host memory **********************************/



/* RSQ - Receive Status Queue 
 *
 * Written by the NICStAR, read by the device driver.
 */

typedef struct ns_rsqe
{
   u32 word_1;
   u32 buffer_handle;
   u32 final_aal5_crc32;
   u32 word_4;
} ns_rsqe;

#define ns_rsqe_vpi(ns_rsqep) \
        ((le32_to_cpu((ns_rsqep)->word_1) & 0x00FF0000) >> 16)
#define ns_rsqe_vci(ns_rsqep) \
        (le32_to_cpu((ns_rsqep)->word_1) & 0x0000FFFF)

#define NS_RSQE_VALID      0x80000000
#define NS_RSQE_NZGFC      0x00004000
#define NS_RSQE_EOPDU      0x00002000
#define NS_RSQE_BUFSIZE    0x00001000
#define NS_RSQE_CONGESTION 0x00000800
#define NS_RSQE_CLP        0x00000400
#define NS_RSQE_CRCERR     0x00000200

#define NS_RSQE_BUFSIZE_SM 0x00000000
#define NS_RSQE_BUFSIZE_LG 0x00001000

#define ns_rsqe_valid(ns_rsqep) \
        (le32_to_cpu((ns_rsqep)->word_4) & NS_RSQE_VALID)
#define ns_rsqe_nzgfc(ns_rsqep) \
        (le32_to_cpu((ns_rsqep)->word_4) & NS_RSQE_NZGFC)
#define ns_rsqe_eopdu(ns_rsqep) \
        (le32_to_cpu((ns_rsqep)->word_4) & NS_RSQE_EOPDU)
#define ns_rsqe_bufsize(ns_rsqep) \
        (le32_to_cpu((ns_rsqep)->word_4) & NS_RSQE_BUFSIZE)
#define ns_rsqe_congestion(ns_rsqep) \
        (le32_to_cpu((ns_rsqep)->word_4) & NS_RSQE_CONGESTION)
#define ns_rsqe_clp(ns_rsqep) \
        (le32_to_cpu((ns_rsqep)->word_4) & NS_RSQE_CLP)
#define ns_rsqe_crcerr(ns_rsqep) \
        (le32_to_cpu((ns_rsqep)->word_4) & NS_RSQE_CRCERR)

#define ns_rsqe_cellcount(ns_rsqep) \
        (le32_to_cpu((ns_rsqep)->word_4) & 0x000001FF)
#define ns_rsqe_init(ns_rsqep) \
        ((ns_rsqep)->word_4 = cpu_to_le32(0x00000000)) 

#define NS_RSQ_NUM_ENTRIES (NS_RSQSIZE / 16)
#define NS_RSQ_ALIGNMENT NS_RSQSIZE



/* RCQ - Raw Cell Queue
 *
 * Written by the NICStAR, read by the device driver.
 */

typedef struct cell_payload
{
   u32 word[12];
} cell_payload;

typedef struct ns_rcqe
{
   u32 word_1;
   u32 word_2;
   u32 word_3;
   u32 word_4;
   cell_payload payload;
} ns_rcqe;

#define NS_RCQE_SIZE 64		/* bytes */

#define ns_rcqe_islast(ns_rcqep) \
        (le32_to_cpu((ns_rcqep)->word_2) != 0x00000000)
#define ns_rcqe_cellheader(ns_rcqep) \
        (le32_to_cpu((ns_rcqep)->word_1))
#define ns_rcqe_nextbufhandle(ns_rcqep) \
        (le32_to_cpu((ns_rcqep)->word_2))



/* SCQ - Segmentation Channel Queue 
 *
 * Written by the device driver, read by the NICStAR.
 */

typedef struct ns_scqe
{
   u32 word_1;
   u32 word_2;
   u32 word_3;
   u32 word_4;
} ns_scqe;

   /* NOTE: SCQ entries can be either a TBD (Transmit Buffer Descriptors)
            or TSR (Transmit Status Requests) */

#define NS_SCQE_TYPE_TBD 0x00000000
#define NS_SCQE_TYPE_TSR 0x80000000


#define NS_TBD_EOPDU 0x40000000
#define NS_TBD_AAL0  0x00000000
#define NS_TBD_AAL34 0x04000000
#define NS_TBD_AAL5  0x08000000

#define NS_TBD_VPI_MASK 0x0FF00000
#define NS_TBD_VCI_MASK 0x000FFFF0
#define NS_TBD_VC_MASK (NS_TBD_VPI_MASK | NS_TBD_VCI_MASK)

#define NS_TBD_VPI_SHIFT 20
#define NS_TBD_VCI_SHIFT 4

#define ns_tbd_mkword_1(flags, m, n, buflen) \
      (cpu_to_le32((flags) | (m) << 23 | (n) << 16 | (buflen)))
#define ns_tbd_mkword_1_novbr(flags, buflen) \
      (cpu_to_le32((flags) | (buflen) | 0x00810000))
#define ns_tbd_mkword_3(control, pdulen) \
      (cpu_to_le32((control) << 16 | (pdulen)))
#define ns_tbd_mkword_4(gfc, vpi, vci, pt, clp) \
      (cpu_to_le32((gfc) << 28 | (vpi) << 20 | (vci) << 4 | (pt) << 1 | (clp)))


#define NS_TSR_INTENABLE 0x20000000

#define NS_TSR_SCDISVBR 0xFFFF		/* Use as scdi for VBR SCD */

#define ns_tsr_mkword_1(flags) \
        (cpu_to_le32(NS_SCQE_TYPE_TSR | (flags)))
#define ns_tsr_mkword_2(scdi, scqi) \
        (cpu_to_le32((scdi) << 16 | 0x00008000 | (scqi)))

#define ns_scqe_is_tsr(ns_scqep) \
        (le32_to_cpu((ns_scqep)->word_1) & NS_SCQE_TYPE_TSR)

#define VBR_SCQ_NUM_ENTRIES 512
#define VBR_SCQSIZE 8192
#define CBR_SCQ_NUM_ENTRIES 64
#define CBR_SCQSIZE 1024

#define NS_SCQE_SIZE 16



/* TSQ - Transmit Status Queue
 *
 * Written by the NICStAR, read by the device driver.
 */

typedef struct ns_tsi
{
   u32 word_1;
   u32 word_2;
} ns_tsi;

   /* NOTE: The first word can be a status word copied from the TSR which
            originated the TSI, or a timer overflow indicator. In this last
	    case, the value of the first word is all zeroes. */

#define NS_TSI_EMPTY          0x80000000
#define NS_TSI_TIMESTAMP_MASK 0x00FFFFFF

#define ns_tsi_isempty(ns_tsip) \
        (le32_to_cpu((ns_tsip)->word_2) & NS_TSI_EMPTY)
#define ns_tsi_gettimestamp(ns_tsip) \
        (le32_to_cpu((ns_tsip)->word_2) & NS_TSI_TIMESTAMP_MASK)

#define ns_tsi_init(ns_tsip) \
        ((ns_tsip)->word_2 = cpu_to_le32(NS_TSI_EMPTY))


#define NS_TSQSIZE 8192
#define NS_TSQ_NUM_ENTRIES 1024
#define NS_TSQ_ALIGNMENT 8192


#define NS_TSI_SCDISVBR NS_TSR_SCDISVBR

#define ns_tsi_tmrof(ns_tsip) \
        (le32_to_cpu((ns_tsip)->word_1) == 0x00000000)
#define ns_tsi_getscdindex(ns_tsip) \
        ((le32_to_cpu((ns_tsip)->word_1) & 0xFFFF0000) >> 16)
#define ns_tsi_getscqpos(ns_tsip) \
        (le32_to_cpu((ns_tsip)->word_1) & 0x00007FFF)



/* NICStAR structures located in local SRAM ***********************************/



/* RCT - Receive Connection Table
 *
 * Written by both the NICStAR and the device driver.
 */

typedef struct ns_rcte
{
   u32 word_1;
   u32 buffer_handle;
   u32 dma_address;
   u32 aal5_crc32;
} ns_rcte;

#define NS_RCTE_BSFB            0x00200000  /* Rev. D only */
#define NS_RCTE_NZGFC           0x00100000
#define NS_RCTE_CONNECTOPEN     0x00080000
#define NS_RCTE_AALMASK         0x00070000
#define NS_RCTE_AAL0            0x00000000
#define NS_RCTE_AAL34           0x00010000
#define NS_RCTE_AAL5            0x00020000
#define NS_RCTE_RCQ             0x00030000
#define NS_RCTE_RAWCELLINTEN    0x00008000
#define NS_RCTE_RXCONSTCELLADDR 0x00004000
#define NS_RCTE_BUFFVALID       0x00002000
#define NS_RCTE_FBDSIZE         0x00001000
#define NS_RCTE_EFCI            0x00000800
#define NS_RCTE_CLP             0x00000400
#define NS_RCTE_CRCERROR        0x00000200
#define NS_RCTE_CELLCOUNT_MASK  0x000001FF

#define NS_RCTE_FBDSIZE_SM 0x00000000
#define NS_RCTE_FBDSIZE_LG 0x00001000

#define NS_RCT_ENTRY_SIZE 4	/* Number of dwords */

   /* NOTE: We could make macros to contruct the first word of the RCTE,
            but that doesn't seem to make much sense... */



/* FBD - Free Buffer Descriptor
 *
 * Written by the device driver using via the command register.
 */

typedef struct ns_fbd
{
   u32 buffer_handle;
   u32 dma_address;
} ns_fbd;




/* TST - Transmit Schedule Table
 *
 * Written by the device driver.
 */

typedef u32 ns_tste;

#define NS_TST_OPCODE_MASK 0x60000000

#define NS_TST_OPCODE_NULL     0x00000000 /* Insert null cell */
#define NS_TST_OPCODE_FIXED    0x20000000 /* Cell from a fixed rate channel */
#define NS_TST_OPCODE_VARIABLE 0x40000000
#define NS_TST_OPCODE_END      0x60000000 /* Jump */

#define ns_tste_make(opcode, sramad) (opcode | sramad)

   /* NOTE:

      - When the opcode is FIXED, sramad specifies the SRAM address of the
        SCD for that fixed rate channel.
      - When the opcode is END, sramad specifies the SRAM address of the
        location of the next TST entry to read.
    */



/* SCD - Segmentation Channel Descriptor
 *
 * Written by both the device driver and the NICStAR
 */

typedef struct ns_scd
{