cpqfctsstructs.h

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/* Copyright(c) 2000, Compaq Computer Corporation
 * Fibre Channel Host Bus Adapter 64-bit, 66MHz PCI 
 * Originally developed and tested on:
 * (front): [chip] Tachyon TS HPFC-5166A/1.2  L2C1090 ...
 *          SP# P225CXCBFIEL6T, Rev XC
 *          SP# 161290-001, Rev XD
 * (back): Board No. 010008-001 A/W Rev X5, FAB REV X5
 *  
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation; either version 2, or (at your option) any
 * later version.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 * Written by Don Zimmerman
*/
#ifndef CPQFCTSSTRUCTS_H
#define CPQFCTSSTRUCTS_H

#include <linux/timer.h>  // timer declaration in our host data
#include <linux/tqueue.h> // task queue sched
#include <asm/atomic.h>
#include "cpqfcTSioctl.h"

#define DbgDelay(secs) { int wait_time; printk( " DbgDelay %ds ", secs); \
                         for( wait_time=jiffies + (secs*HZ); \
		         wait_time > jiffies ;) ; }
#define CPQFCTS_DRIVER_VER(maj,min,submin) ((maj<<16)|(min<<8)|(submin))
#define VER_MAJOR 1
#define VER_MINOR 3
#define VER_SUBMINOR 4

// Macros for kernel (esp. SMP) tracing using a PCI analyzer
// (e.g. x86).
//#define PCI_KERNEL_TRACE
#ifdef PCI_KERNEL_TRACE
#define PCI_TRACE(x) inl( fcChip->Registers.IOBaseL +x);
#define PCI_TRACEO(x,y) outl( x, (fcChip->Registers.IOBaseL +y));
#else

#define PCI_TRACE(x) 
#define PCI_TRACEO(x,y)
#endif

			 
//#define DEBUG_CMND 1   // debug output for Linux Scsi CDBs
//#define DUMMYCMND_DBG 1

//#define DEBUG_CPQFCTS 1
//#undef DEBUG_CPQFCTS 
#ifdef DEBUG_CPQFCTS
#define ENTER(x)	printk("cpqfcts : entering %s()\n", x);
#define LEAVE(x)	printk("cpqfcts : leaving %s()\n", x);
#define DEBUG(x)	x
#else
#define ENTER(x)
#define LEAVE(x)
#define DEBUG(x)
#endif				/* DEBUG_CPQFCTS */

//#define DEBUG_CPQFCTS_PCI 1
//#undef DEBUG_CPQFCTS_PCI
#if DEBUG_CPQFCTS_PCI
#define DEBUG_PCI(x)	x
#else
#define DEBUG_PCI(x)
#endif				/* DEBUG_CPQFCTS_PCI */

#define STACHLITE66_TS12  "Compaq FibreChannel HBA Tachyon TS HPFC-5166A/1.2"
#define STACHLITE66_TS13  "Compaq FibreChannel HBA Tachyon TS HPFC-5166A/1.3"
#define STACHLITE_UNKNOWN "Compaq FibreChannel HBA Tachyon Chip/Board Ver??"
#define SAGILENT_XL2_21   "Agilent FC HBA, Tachyon XL2 HPFC-5200B/2.1"

// PDA is Peripheral Device Address, VSA is Volume Set Addressing
// Linux SCSI parameters
#define CPQFCTS_MAX_TARGET_ID 64
#define CPQFCTS_MAX_LUN 8    // The RA-4x00 supports 32 (Linux SCSI supports 8)
#define CPQFCTS_MAX_CHANNEL 0 // One FC port on cpqfcTS HBA

#define CPQFCTS_CMD_PER_LUN 15 // power of 2 -1, must be >0 
#define CPQFCTS_REQ_QUEUE_LEN (TACH_SEST_LEN/2) // must be < TACH_SEST_LEN

#define LinuxVersionCode(v, p, s) (((v)<<16)+((p)<<8)+(s))
#ifndef DECLARE_MUTEX_LOCKED
#define DECLARE_MUTEX_LOCKED(sem) struct semaphore sem = MUTEX_LOCKED
#endif

#define DEV_NAME "cpqfcTS"

#define CPQ_DEVICE_ID     0xA0FC
#define AGILENT_XL2_ID    0x1029

typedef struct
{
  __u16 vendor_id;
  __u16 device_id;
} SupportedPCIcards;
			 
// nn:nn denotes bit field
                            // TachyonHeader struct def.
                            // the fields shared with ODB
                            // need to have same value




#ifndef BYTE
//typedef UCHAR BYTE;
typedef __u8 BYTE;
#endif
#ifndef UCHAR
typedef __u8 UCHAR;
#endif
#ifndef LONG
typedef __s32 LONG;
#endif
#ifndef ULONG
typedef __u32 ULONG;
#endif
#ifndef PVOID
typedef void * PVOID;
#endif
#ifndef USHORT
typedef __u16 USHORT;
#endif
#ifndef BOOLEAN
typedef __u8 BOOLEAN;
#endif


// macro for FC-PH reject codes
// payload format for LS_RJT (FC payloads are big endian):
//     byte  0         1         2         3  (MSB)
// DWORD 0   01        00        00        00
// DWORD 1   resvd     code      expl.     vendor

#define LS_RJT_REASON( code, expl) (( code<<8) | (expl <<16))


#define TachLiteSTATUS 0x12

// Fibre Channel EXCHANGE status codes for Tachyon chips/ driver software
// 32-bit ERROR word defines
#define INVALID_ARGS 0x1
#define LNKDWN_OSLS  0x2
#define LNKDWN_LASER 0x4
#define OUTQUE_FULL  0x8
#define DRIVERQ_FULL 0x10
#define SEST_FULL    0x20
#define BAD_ALPA     0x40
#define OVERFLOW     0x80  // inbound CM
#define COUNT_ERROR     0x100  // inbound CM
#define LINKFAIL_RX     0x200  // inbound CM
#define ABORTSEQ_NOTIFY 0x400  // outbound CM
#define LINKFAIL_TX     0x800  // outbound CM
#define HOSTPROG_ERR     0x1000  // outbound CM
#define FRAME_TO         0x2000  // outbound CM
#define INV_ENTRY        0x4000  // outbound CM
#define SESTPROG_ERR     0x8000  // outbound CM
#define OUTBOUND_TIMEOUT 0x10000L // timeout waiting for Tachyon outbound CM
#define INITIATOR_ABORT  0x20000L // initiator exchange timeout or O/S ABORT
#define MEMPOOL_FAIL     0x40000L // O/S memory pool allocation failed
#define FC2_TIMEOUT      0x80000L // driver timeout for lost frames
#define TARGET_ABORT     0x100000L // ABTS received from FC port
#define EXCHANGE_QUEUED  0x200000L // e.g. Link State was LDn on fcStart
#define PORTID_CHANGED   0x400000L // fc Port address changed
#define DEVICE_REMOVED   0x800000L // fc Port address changed
// Several error scenarios result in SEST Exchange frames 
// unexpectedly arriving in the SFQ
#define SFQ_FRAME        0x1000000L // SFQ frames from open Exchange

// Maximum number of Host Bus Adapters (HBA) / controllers supported
// only important for mem allocation dimensions - increase as necessary

#define MAX_ADAPTERS 8
#define MAX_RX_PAYLOAD 1024  // hardware dependent max frame payload
// Tach header struc defines
#define SOFi3 0x7
#define SOFf  0x8
#define SOFn3 0xB
#define EOFn  0x5
#define EOFt  0x6

// FCP R_CTL defines
#define FCP_CMND 0x6
#define FCP_XFER_RDY 0x5
#define FCP_RSP 0x7
#define FCP_RESPONSE 0x777 // (arbitrary #)
#define NEED_FCP_RSP 0x77  // (arbitrary #)
#define FCP_DATA 0x1

#define RESET_TACH 0x100 // Reset Tachyon/TachLite
#define SCSI_IWE 0x2000  // initiator write entry (for SEST)
#define SCSI_IRE 0x3000  // initiator read entry (for SEST)
#define SCSI_TRE 0x400  // target read entry (for SEST)
#define SCSI_TWE 0x500  // target write entry (for SEST)
#define TOGGLE_LASER 0x800
#define LIP 0x900
#define CLEAR_FCPORTS 99 // (arbitrary #) free mem for Logged in ports
#define FMINIT 0x707     // (arbitrary) for Frame Manager Init command

// BLS == Basic Link Service
// ELS == Extended Link Service
#define BLS_NOP 4
#define BLS_ABTS 0x10   // FC-PH Basic Link Service Abort Sequence
#define BLS_ABTS_ACC 0x100  // FC-PH Basic Link Service Abort Sequence Accept
#define BLS_ABTS_RJT 0x101  // FC-PH Basic Link Service Abort Sequence Reject
#define ELS_PLOGI 0x03  // FC-PH Port Login (arbitrary assign)
#define ELS_SCR   0x70  // (arb assign) State Change Registration (Fabric)
#define FCS_NSR   0x72  // (arb assign) Name Service Request (Fabric)
#define ELS_FLOGI 0x44  // (arb assign) Fabric Login
#define ELS_FDISC 0x41  // (arb assign) Fabric Discovery (Login)
#define ELS_PDISC 0x50  // FC-PH2 Port Discovery
#define ELS_ABTX  0x06  // FC-PH Abort Exchange 
#define ELS_LOGO 0x05   // FC-PH Port Logout
#define ELS_PRLI 0x20   // FCP-SCSI Process Login
#define ELS_PRLO 0x21   // FCP-SCSI Process Logout
#define ELS_LOGO_ACC 0x07   // {FC-PH} Port Logout Accept
#define ELS_PLOGI_ACC 0x08  // {FC-PH} Port Login Accept
#define ELS_ACC 0x18        // {FC-PH} (generic) ACCept
#define ELS_PRLI_ACC 0x22  // {FCP-SCSI} Process Login Accept
#define ELS_RJT 0x1000000
#define SCSI_REPORT_LUNS 0x0A0
#define REPORT_LUNS 0xA0 // SCSI-3 command op-code

#define ELS_LILP_FRAME 0x00000711 // 1st payload word of LILP frame

#define SFQ_UNASSISTED_FCP  1  // ICM, DWord3, "Type" unassisted FCP
#define SFQ_UNKNOWN         0x31 // (arbitrary) ICM, DWord3, "Type" unknown

// these "LINK" bits refer to loop or non-loop
#define LINKACTIVE 0x2    // fcLinkQ type - LINK UP Tachyon FM 'Lup' bit set
#define LINKDOWN 0xf2     // fcLinkQ type - LINK DOWN Tachyon FM 'Ldn' bit set

//#define VOLUME_SET_ADDRESSING 1 // "channel" or "bus" 1

typedef struct      // 32 bytes hdr ONLY (e.g. FCP_DATA buffer for SEST)
{
  ULONG reserved;   // dword 0 (don't use)
  ULONG sof_eof;
  ULONG d_id;       // dword 2 - 31:24 R_CTL, 23:0 D_ID
  ULONG s_id;       // dword 3 - 31:24 CS_CTL, 23:0 S_ID
  ULONG f_ctl;      // dword 4 - 31:24 Type,  23:0 F_CTL
  ULONG seq_cnt;    // dword 5 - 31:24 SEQ_ID, 23:16 DF_CTL, 15:0 SEQ_CNT
  ULONG ox_rx_id;   // dword 6 - 31:16 OX_ID,  15:0 RX_ID
  ULONG ro;         // dword 7 - relative offset
} TachFCHDR;

                    // NOTE!! the following struct MUST be 64 bytes.
typedef struct      // 32 bytes hdr + 32 bytes payload
{
  ULONG reserved;   // dword 0 (don't use - must clear to 0)
  ULONG sof_eof;    // dword 1 - 31:24 SOF:EOF, UAM,CLS, LCr, TFV, TimeStamp
  ULONG d_id;       // dword 2 - 31:24 R_CTL, 23:0 D_ID
  ULONG s_id;       // dword 3 - 31:24 CS_CTL, 23:0 S_ID
  ULONG f_ctl;      // dword 4 - 31:24 Type,  23:0 F_CTL
  ULONG seq_cnt;    // dword 5 - 31:24 SEQ_ID, 23:16 DF_CTL, 15:0 SEQ_CNT
  ULONG ox_rx_id;   // dword 6 - 31:16 OX_ID,  15:0 RX_ID
  ULONG ro;  // dword 7 - relative offset
//---------
  __u32 pl[8];              // dwords 8-15 frame data payload
} TachFCHDR_CMND;


typedef struct      // 32 bytes hdr + 120 bytes payload
{
  ULONG reserved;   // dword 0 (don't use - must clear to 0)
  ULONG sof_eof;    // dword 1 - 31:24 SOF:EOF, UAM,CLS, LCr, TFV, TimeStamp
  ULONG d_id;       // dword 2 - 31:24 R_CTL, 23:0 D_ID
  ULONG s_id;       // dword 3 - 31:24 CS_CTL, 23:0 S_ID
  ULONG f_ctl;      // dword 4 - 31:24 Type,  23:0 F_CTL
  ULONG seq_cnt;    // dword 5 - 31:24 SEQ_ID, 23:16 DF_CTL, 15:0 SEQ_CNT
  ULONG ox_rx_id;   // dword 6 - 31:16 OX_ID,  15:0 RX_ID
  ULONG ro;  // dword 7 - relative offset
//---------
  __u32 pl[30];              // largest necessary payload (for LOGIN cmnds)
} TachFCHDR_GCMND;

typedef struct      // 32 bytes hdr + 64 bytes payload
{
  ULONG reserved;   // dword 0 (don't use)
  ULONG sof_eof;
  ULONG d_id;       // dword 2 - 31:24 R_CTL, 23:0 D_ID
  ULONG s_id;       // dword 3 - 31:24 CS_CTL, 23:0 S_ID
  ULONG f_ctl;      // dword 4 - 31:24 Type,  23:0 F_CTL
  ULONG seq_cnt;    // dword 5 - 31:24 SEQ_ID, 23:16 DF_CTL, 15:0 SEQ_CNT
  ULONG ox_rx_id;   // dword 6 - 31:16 OX_ID,  15:0 RX_ID
  ULONG ro;  // dword 7 - relative offset
//---------
  __u32 pl[18]; // payload for FCP-RSP (response buffer) RA-4x00 is 72bytes
} TachFCHDR_RSP;






// Inbound Message Queue structures...
typedef struct              // each entry 8 words (32 bytes)
{
  ULONG type;               // IMQ completion message types
  ULONG word[7];            // remainder of structure
                            // interpreted by IMQ type
} TachyonIMQE;


// Queues for TachLite not in original Tachyon
// ERQ       - Exchange Request Queue (for outbound commands)
// SFQ       - Single Frame Queue (for incoming frames)

                            // Define Tachyon Outbound Command Que
                            // (Since many Tachyon registers are Read
                            // only, maintain copies for debugging)
                            // most Tach ques need power-of-2 sizes,
                            // where registers are loaded with po2 -1
#define TACH_SEST_LEN 512   // TachLite SEST

#define ELS_EXCHANGES 64    // e.g. PLOGI, RSCN, ...
// define the total number of outstanding (simultaneous) exchanges
#define TACH_MAX_XID (TACH_SEST_LEN + ELS_EXCHANGES)  // ELS exchanges

#define ERQ_LEN 128         // power of 2, max 4096

// Inbound Message Queue structures...
#define IMQ_LEN 512              // minimum 4 entries [(power of 2) - 1]
typedef struct                   // 8 words - 32 bytes
{
  TachyonIMQE QEntry[IMQ_LEN];
  ULONG producerIndex;   // IMQ Producer Index register
                                 // @32 byte align
  ULONG consumerIndex;   // Consumer Index register (in Tachyon)
  ULONG length;          // Length register
  ULONG base;
} TachyonIMQ;                    // @ 32 * IMQ_LEN align



typedef struct           // inbound completion message
{
  ULONG Type;
  ULONG Index;
  ULONG TransferLength;
} TachyonInbCM;



// arbitrary numeric tags for TL structures
#define TL_FCHS 1  // TachLite Fibre Channel Header Structure
#define TL_IWE 2  // initiator write entry (for SEST)
#define TL_TWE 3  // target write entry (for SEST)
#define TL_IRE 4  // initiator read entry (for SEST)
#define TL_TRE 5  // target read entry (for SEST)
#define TL_IRB 6  // I/O request block

                                // for INCOMING frames
#define SFQ_LEN 32              // minimum 32 entries, max 4096

typedef struct                  // Single Frame Que
{
  TachFCHDR_CMND QEntry[SFQ_LEN]; // must be 64 bytes!!
  ULONG producerIndex;   // IMQ Producer Index register
                                 // @32 byte align
  ULONG consumerIndex;   // Consumer Index register (in Tachyon)
  ULONG length;          // Length register
  ULONG base;
} TachLiteSFQ;


typedef struct                 // I/O Request Block flags
{
  UCHAR  BRD : 1;
  UCHAR      : 1; // reserved
  UCHAR  SFA : 1;
  UCHAR  DNC : 1;
  UCHAR  DIN : 1;
  UCHAR  DCM : 1;
  UCHAR  CTS : 1;
  UCHAR  SBV : 1;  // IRB entry valid - IRB'B' only
} IRBflags;

typedef struct                  // I/O Request Block
{                          // Request 'A'
  ULONG Req_A_SFS_Len;     // total frame len (hdr + payload), min 32
  ULONG Req_A_SFS_Addr;    // 32-bit pointer to FCHS struct (to be sent)
  ULONG Req_A_SFS_D_ID;    // 24-bit FC destination (i.e. 8 bit al_pa)
  ULONG Req_A_Trans_ID;    // X_ID (OX_ID or RX_ID) and/or Index in SEST
                           // Request 'B'
  ULONG Req_B_SFS_Len;     // total frame len (hdr + payload), min 32
  ULONG Req_B_SFS_Addr;    // 32-bit pointer to FCHS struct (to be sent)
  ULONG Req_B_SFS_D_ID;    // 24-bit FC destination (i.e. 8 bit al_pa)
  ULONG Req_B_Trans_ID;    // X_ID (OX_ID or RX_ID) and/or Index in SEST
} TachLiteIRB;


typedef struct           // TachLite placeholder for IRBs
{                        // aligned @sizeof(ERQ) for TachLite
                         // MAX commands is sum of SEST len and ERQ
                         // we know that each SEST entry requires an
                         // IRB (ERQ) entry; in addition, we provide
                         // ERQ_LEN
  TachLiteIRB QEntry[ERQ_LEN]; // Base register; entries 32 bytes ea.
  ULONG consumerIndex;   // Consumer Index register
  ULONG producerIndex;   // ERQ Producer Index register
  ULONG length;          // Length register
  ULONG base;            // copy of base ptr for debug
                         // struct is sized for largest expected cmnd (LOGIN)
} TachLiteERQ;


#define TL_MAX_SGPAGES 4  // arbitrary limit to # of TL Ext. S/G pages
                          // stores array of allocated page blocks used
                          // in extended S/G lists.  Affects amount of static
                          // memory consumed by driver.
#define TL_EXT_SG_PAGE_COUNT 256  // Number of Extended Scatter/Gather a/l PAIRS
                                  // Tachyon register (IOBaseU 0x68)
                                  // power-of-2 value ONLY!  4 min, 256 max

                          // byte len is #Pairs * 2 ULONG/Pair * 4 bytes/ULONG
#define TL_EXT_SG_PAGE_BYTELEN (TL_EXT_SG_PAGE_COUNT *2 *4)



// SEST entry types: IWE, IRE, TWE, TRE
typedef struct 
{
  ULONG Hdr_Len;
  ULONG Hdr_Addr;
  ULONG RSP_Len;
  ULONG RSP_Addr;
  ULONG Buff_Off;
  ULONG Link;
  ULONG RX_ID;
  ULONG Data_Len;
  ULONG Exp_RO;
  ULONG Exp_Byte_Cnt;
   // --- extended/local Gather Len/Address pairs
  ULONG GLen1;
  ULONG GAddr1;
  ULONG GLen2;
  ULONG GAddr2;
  ULONG GLen3;
  ULONG GAddr3;
} TachLiteIWE;


typedef struct 
{
  ULONG Seq_Accum;
  ULONG reserved;       // must clear to 0
  ULONG RSP_Len;
  ULONG RSP_Addr;
  ULONG Buff_Off;
  ULONG Buff_Index;           // ULONG 5
  ULONG Exp_RO;
  ULONG Byte_Count;
  ULONG reserved_;      // ULONG 8
  ULONG Exp_Byte_Cnt;
   // --- extended/local Scatter Len/Address pairs
  ULONG SLen1;
  ULONG SAddr1;
  ULONG SLen2;
  ULONG SAddr2;
  ULONG SLen3;
  ULONG SAddr3;
} TachLiteIRE;


typedef struct          // Target Write Entry
{
  ULONG Seq_Accum;      // dword 0
  ULONG reserved;       // dword 1  must clear to 0
  ULONG Remote_Node_ID;
  ULONG reserved1;      // dword 3  must clear to 0
  ULONG Buff_Off;
  ULONG Buff_Index;     // ULONG 5
  ULONG Exp_RO;
  ULONG Byte_Count;
  ULONG reserved_;      // ULONG 8
  ULONG Exp_Byte_Cnt;
   // --- extended/local Scatter Len/Address pairs
  ULONG SLen1;
  ULONG SAddr1;
  ULONG SLen2;
  ULONG SAddr2;
  ULONG SLen3;
  ULONG SAddr3;
} TachLiteTWE;

typedef struct      
{
  ULONG Hdr_Len;
  ULONG Hdr_Addr;
  ULONG RSP_Len;        // DWord 2
  ULONG RSP_Addr;
  ULONG Buff_Off;
  ULONG Buff_Index;     // DWord 5