qlogicfc.c

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/*
 * QLogic ISP2x00 SCSI-FCP
 * Written by Erik H. Moe, [e-mail]
 * Copyright 1995, Erik H. Moe
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation; either version 2, or (at your option) any
 * later version.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 */

/* Renamed and updated to 1.3.x by Michael Griffith <[e-mail]> */

/* This is a version of the isp1020 driver which was modified by
 * Chris Loveland <[e-mail]> to support the isp2100 and isp2200
 *
 * Big endian support and dynamic DMA mapping added
 * by Jakub Jelinek <[e-mail]>.
 */

/*
 * $Date: 1995/09/22 02:23:15 $
 * $Revision: 0.5 $
 *
 * $Log: isp1020.c,v $
 * Revision 0.5  1995/09/22  02:23:15  root
 * do auto request sense
 *
 * Revision 0.4  1995/08/07  04:44:33  root
 * supply firmware with driver.
 * numerous bug fixes/general cleanup of code.
 *
 * Revision 0.3  1995/07/16  16:15:39  root
 * added reset/abort code.
 *
 * Revision 0.2  1995/06/29  03:14:19  root
 * fixed biosparam.
 * added queue protocol.
 *
 * Revision 0.1  1995/06/25  01:55:45  root
 * Initial release.
 *
 */

#include <linux/blk.h>
#include <linux/kernel.h>
#include <linux/string.h>
#include <linux/ioport.h>
#include <linux/sched.h>
#include <linux/types.h>
#include <linux/pci.h>
#include <linux/delay.h>
#include <linux/unistd.h>
#include <linux/spinlock.h>
#include <asm/io.h>
#include <asm/irq.h>

#include "sd.h"
#include "hosts.h"

#if 1
/* Once pci64_ DMA mapping interface is in, kill this. */
typedef dma_addr_t dma64_addr_t;
#define pci64_alloc_consistent(d,s,p) pci_alloc_consistent((d),(s),(p))
#define pci64_free_consistent(d,s,c,a) pci_free_consistent((d),(s),(c),(a))
#define pci64_map_single(d,c,s,dir) pci_map_single((d),(c),(s),(dir))
#define pci64_map_sg(d,s,n,dir) pci_map_sg((d),(s),(n),(dir))
#define pci64_unmap_single(d,a,s,dir) pci_unmap_single((d),(a),(s),(dir))
#define pci64_unmap_sg(d,s,n,dir) pci_unmap_sg((d),(s),(n),(dir))
#if BITS_PER_LONG > 32
#define pci64_dma_hi32(a) ((u32) (0xffffffff & (((u64)(a))>>32)))
#define pci64_dma_lo32(a) ((u32) (0xffffffff & (((u64)(a)))))
#else
#define pci64_dma_hi32(a) 0
#define pci64_dma_lo32(a) (a)
#endif	/* BITS_PER_LONG */
#define pci64_dma_build(hi,lo) (lo)
#define sg_dma64_address(s) sg_dma_address(s)
#define sg_dma64_len(s) sg_dma_len(s)
#if BITS_PER_LONG > 32
#define PCI64_DMA_BITS 64
#else
#define PCI64_DMA_BITS	32
#endif 	/* BITS_PER_LONG */
#endif

#include "qlogicfc.h"

/* Configuration section **************************************************** */

/* Set the following macro to 1 to reload the ISP2x00's firmware.  This is
   version 1.17.30 of the isp2100's firmware and version 2.00.40 of the 
   isp2200's firmware. 
*/

#define RELOAD_FIRMWARE		1

#define USE_NVRAM_DEFAULTS      1

#define ISP2x00_PORTDB          1

/* Set the following to 1 to include fabric support, fabric support is 
 * currently not as well tested as the other aspects of the driver */

#define ISP2x00_FABRIC          1

/*  Macros used for debugging */
#define DEBUG_ISP2x00		0
#define DEBUG_ISP2x00_INT	0
#define DEBUG_ISP2x00_INTR	0
#define DEBUG_ISP2x00_SETUP	0
#define DEBUG_ISP2x00_FABRIC    0
#define TRACE_ISP 		0 


#define DEFAULT_LOOP_COUNT	1000000000

/* End Configuration section ************************************************ */

#include <linux/module.h>

#if TRACE_ISP

#define TRACE_BUF_LEN	(32*1024)

struct {
	u_long next;
	struct {
		u_long time;
		u_int index;
		u_int addr;
		u_char *name;
	} buf[TRACE_BUF_LEN];
} trace;

#define TRACE(w, i, a)						\
{								\
	unsigned long flags;					\
								\
	save_flags(flags);					\
	cli();							\
	trace.buf[trace.next].name  = (w);			\
	trace.buf[trace.next].time  = jiffies;			\
	trace.buf[trace.next].index = (i);			\
	trace.buf[trace.next].addr  = (long) (a);		\
	trace.next = (trace.next + 1) & (TRACE_BUF_LEN - 1);	\
	restore_flags(flags);					\
}

#else
#define TRACE(w, i, a)
#endif

#if DEBUG_ISP2x00_FABRIC
#define DEBUG_FABRIC(x)	x
#else
#define DEBUG_FABRIC(x)
#endif				/* DEBUG_ISP2x00_FABRIC */


#if DEBUG_ISP2x00
#define ENTER(x)	printk("isp2x00 : entering %s()\n", x);
#define LEAVE(x)	printk("isp2x00 : leaving %s()\n", x);
#define DEBUG(x)	x
#else
#define ENTER(x)
#define LEAVE(x)
#define DEBUG(x)
#endif				/* DEBUG_ISP2x00 */

#if DEBUG_ISP2x00_INTR
#define ENTER_INTR(x)	printk("isp2x00 : entering %s()\n", x);
#define LEAVE_INTR(x)	printk("isp2x00 : leaving %s()\n", x);
#define DEBUG_INTR(x)	x
#else
#define ENTER_INTR(x)
#define LEAVE_INTR(x)
#define DEBUG_INTR(x)
#endif				/* DEBUG ISP2x00_INTR */


#define ISP2100_REV_ID1	       1
#define ISP2100_REV_ID3        3
#define ISP2200_REV_ID5        5

/* host configuration and control registers */
#define HOST_HCCR	0xc0	/* host command and control */

/* pci bus interface registers */
#define FLASH_BIOS_ADDR	0x00
#define FLASH_BIOS_DATA	0x02
#define ISP_CTRL_STATUS	0x06	/* configuration register #1 */
#define PCI_INTER_CTL	0x08	/* pci interupt control */
#define PCI_INTER_STS	0x0a	/* pci interupt status */
#define PCI_SEMAPHORE	0x0c	/* pci semaphore */
#define PCI_NVRAM	0x0e	/* pci nvram interface */

/* mailbox registers */
#define MBOX0		0x10	/* mailbox 0 */
#define MBOX1		0x12	/* mailbox 1 */
#define MBOX2		0x14	/* mailbox 2 */
#define MBOX3		0x16	/* mailbox 3 */
#define MBOX4		0x18	/* mailbox 4 */
#define MBOX5		0x1a	/* mailbox 5 */
#define MBOX6		0x1c	/* mailbox 6 */
#define MBOX7		0x1e	/* mailbox 7 */

/* mailbox command complete status codes */
#define MBOX_COMMAND_COMPLETE		0x4000
#define INVALID_COMMAND			0x4001
#define HOST_INTERFACE_ERROR		0x4002
#define TEST_FAILED			0x4003
#define COMMAND_ERROR			0x4005
#define COMMAND_PARAM_ERROR		0x4006
#define PORT_ID_USED                    0x4007
#define LOOP_ID_USED                    0x4008
#define ALL_IDS_USED                    0x4009

/* async event status codes */
#define RESET_DETECTED  		0x8001
#define SYSTEM_ERROR			0x8002
#define REQUEST_TRANSFER_ERROR		0x8003
#define RESPONSE_TRANSFER_ERROR		0x8004
#define REQUEST_QUEUE_WAKEUP		0x8005
#define LIP_OCCURED                     0x8010
#define LOOP_UP                         0x8011
#define LOOP_DOWN                       0x8012
#define LIP_RECEIVED                    0x8013
#define PORT_DB_CHANGED                 0x8014
#define CHANGE_NOTIFICATION             0x8015
#define SCSI_COMMAND_COMPLETE           0x8020
#define POINT_TO_POINT_UP               0x8030
#define CONNECTION_MODE                 0x8036

struct Entry_header {
	u_char entry_type;
	u_char entry_cnt;
	u_char sys_def_1;
	u_char flags;
};

/* entry header type commands */
#if PCI64_DMA_BITS > 32
#define ENTRY_COMMAND		0x19
#define ENTRY_CONTINUATION	0x0a
#else
#define ENTRY_COMMAND		0x11
#define ENTRY_CONTINUATION	0x02
#endif

#define ENTRY_STATUS		0x03
#define ENTRY_MARKER		0x04


/* entry header flag definitions */
#define EFLAG_BUSY		2
#define EFLAG_BAD_HEADER	4
#define EFLAG_BAD_PAYLOAD	8

#if PCI64_DMA_BITS > 32

struct dataseg {
	u_int d_base;
	u_int d_base_hi;
	u_int d_count;
};

#else

struct dataseg {
	u_int d_base;
	u_int d_count;
};

#endif

struct Command_Entry {
	struct Entry_header hdr;
	u_int handle;
	u_char target_lun;
	u_char target_id;
	u_short expanded_lun;
	u_short control_flags;
	u_short rsvd2;
	u_short time_out;
	u_short segment_cnt;
	u_char cdb[16];
	u_int total_byte_cnt;
	struct dataseg dataseg[DATASEGS_PER_COMMAND];
};

/* command entry control flag definitions */
#define CFLAG_NODISC		0x01
#define CFLAG_HEAD_TAG		0x02
#define CFLAG_ORDERED_TAG	0x04
#define CFLAG_SIMPLE_TAG	0x08
#define CFLAG_TAR_RTN		0x10
#define CFLAG_READ		0x20
#define CFLAG_WRITE		0x40

#if PCI64_DMA_BITS > 32
struct Continuation_Entry {
	struct Entry_header hdr;
	struct dataseg dataseg[DATASEGS_PER_CONT];
};
#else
struct Continuation_Entry {
	struct Entry_header hdr;
        u32 rsvd;
	struct dataseg dataseg[DATASEGS_PER_CONT];
};
#endif

struct Marker_Entry {
	struct Entry_header hdr;
	u_int reserved;
	u_char target_lun;
	u_char target_id;
	u_char modifier;
	u_char expanded_lun;
	u_char rsvds[52];
};

/* marker entry modifier definitions */
#define SYNC_DEVICE	0
#define SYNC_TARGET	1
#define SYNC_ALL	2

struct Status_Entry {
	struct Entry_header hdr;
	u_int handle;
	u_short scsi_status;
	u_short completion_status;
	u_short state_flags;
	u_short status_flags;
	u_short res_info_len;
	u_short req_sense_len;
	u_int residual;
	u_char res_info[8];
	u_char req_sense_data[32];
};

/* status entry completion status definitions */
#define CS_COMPLETE			0x0000
#define CS_DMA_ERROR			0x0002
#define CS_RESET_OCCURRED		0x0004
#define CS_ABORTED			0x0005
#define CS_TIMEOUT			0x0006
#define CS_DATA_OVERRUN			0x0007
#define CS_DATA_UNDERRUN		0x0015
#define CS_QUEUE_FULL			0x001c
#define CS_PORT_UNAVAILABLE             0x0028
#define CS_PORT_LOGGED_OUT              0x0029
#define CS_PORT_CONFIG_CHANGED		0x002a

/* status entry state flag definitions */
#define SF_SENT_CDB			0x0400
#define SF_TRANSFERRED_DATA		0x0800
#define SF_GOT_STATUS			0x1000

/* status entry status flag definitions */
#define STF_BUS_RESET			0x0008
#define STF_DEVICE_RESET		0x0010
#define STF_ABORTED			0x0020
#define STF_TIMEOUT			0x0040

/* interupt control commands */
#define ISP_EN_INT			0x8000
#define ISP_EN_RISC			0x0008

/* host control commands */
#define HCCR_NOP			0x0000
#define HCCR_RESET			0x1000
#define HCCR_PAUSE			0x2000
#define HCCR_RELEASE			0x3000
#define HCCR_SINGLE_STEP		0x4000
#define HCCR_SET_HOST_INTR		0x5000
#define HCCR_CLEAR_HOST_INTR		0x6000
#define HCCR_CLEAR_RISC_INTR		0x7000
#define HCCR_BP_ENABLE			0x8000
#define HCCR_BIOS_DISABLE		0x9000
#define HCCR_TEST_MODE			0xf000

#define RISC_BUSY			0x0004

/* mailbox commands */
#define MBOX_NO_OP			0x0000
#define MBOX_LOAD_RAM			0x0001
#define MBOX_EXEC_FIRMWARE		0x0002
#define MBOX_DUMP_RAM			0x0003
#define MBOX_WRITE_RAM_WORD		0x0004
#define MBOX_READ_RAM_WORD		0x0005
#define MBOX_MAILBOX_REG_TEST		0x0006
#define MBOX_VERIFY_CHECKSUM		0x0007
#define MBOX_ABOUT_FIRMWARE		0x0008
#define MBOX_LOAD_RISC_RAM              0x0009
#define MBOX_DUMP_RISC_RAM              0x000a
#define MBOX_CHECK_FIRMWARE		0x000e
#define MBOX_INIT_REQ_QUEUE		0x0010
#define MBOX_INIT_RES_QUEUE		0x0011
#define MBOX_EXECUTE_IOCB		0x0012
#define MBOX_WAKE_UP			0x0013
#define MBOX_STOP_FIRMWARE		0x0014
#define MBOX_ABORT_IOCB			0x0015
#define MBOX_ABORT_DEVICE		0x0016
#define MBOX_ABORT_TARGET		0x0017
#define MBOX_BUS_RESET			0x0018
#define MBOX_STOP_QUEUE			0x0019
#define MBOX_START_QUEUE		0x001a
#define MBOX_SINGLE_STEP_QUEUE		0x001b
#define MBOX_ABORT_QUEUE		0x001c
#define MBOX_GET_DEV_QUEUE_STATUS	0x001d
#define MBOX_GET_FIRMWARE_STATUS	0x001f
#define MBOX_GET_INIT_SCSI_ID		0x0020
#define MBOX_GET_RETRY_COUNT		0x0022
#define MBOX_GET_TARGET_PARAMS		0x0028
#define MBOX_GET_DEV_QUEUE_PARAMS	0x0029
#define MBOX_SET_RETRY_COUNT		0x0032
#define MBOX_SET_TARGET_PARAMS		0x0038
#define MBOX_SET_DEV_QUEUE_PARAMS	0x0039
#define MBOX_EXECUTE_IOCB64             0x0054
#define MBOX_INIT_FIRMWARE              0x0060
#define MBOX_GET_INIT_CB                0x0061
#define MBOX_INIT_LIP			0x0062
#define MBOX_GET_POS_MAP                0x0063
#define MBOX_GET_PORT_DB                0x0064
#define MBOX_CLEAR_ACA                  0x0065
#define MBOX_TARGET_RESET               0x0066
#define MBOX_CLEAR_TASK_SET             0x0067
#define MBOX_ABORT_TASK_SET             0x0068
#define MBOX_GET_FIRMWARE_STATE         0x0069
#define MBOX_GET_PORT_NAME              0x006a
#define MBOX_SEND_SNS                   0x006e
#define MBOX_PORT_LOGIN                 0x006f
#define MBOX_SEND_CHANGE_REQUEST        0x0070
#define MBOX_PORT_LOGOUT                0x0071