flashpoint.c

Linux内核源代码 为压缩文件 是<<Linux内核>>一书中的源代码

      #define  S_SCSI_PHZ        (BIT(2)+BIT(1)+BIT(0))
      #define  S_CMD_PH          (BIT(2)              )
      #define  S_MSGO_PH         (BIT(2)+BIT(1)       )
      #define  S_STAT_PH         (BIT(2)       +BIT(0))
      #define  S_MSGI_PH         (BIT(2)+BIT(1)+BIT(0))
      #define  S_DATAI_PH        (              BIT(0))
      #define  S_DATAO_PH        0x00
      #define  S_ILL_PH          (       BIT(1)       )

   #define  hp_scsictrl_0        0x45

      #define  NO_ARB            BIT(7)
      #define  SEL_TAR           BIT(6)
      #define  ENA_ATN           BIT(4)
      #define  ENA_RESEL         BIT(2)
      #define  SCSI_RST          BIT(1)
      #define  ENA_SCAM_SEL      BIT(0)



   #define  hp_portctrl_0        0x46

      #define  SCSI_PORT         BIT(7)
      #define  SCSI_INBIT        BIT(6)
      #define  DMA_PORT          BIT(5)
      #define  DMA_RD            BIT(4)
      #define  HOST_PORT         BIT(3)
      #define  HOST_WRT          BIT(2)
      #define  SCSI_BUS_EN       BIT(1)
      #define  START_TO          BIT(0)

   #define  hp_scsireset         0x47

      #define  SCSI_TAR          BIT(7)
      #define  SCSI_INI          BIT(6)
      #define  SCAM_EN           BIT(5)
      #define  ACK_HOLD          BIT(4)
      #define  DMA_RESET         BIT(3)
      #define  HPSCSI_RESET      BIT(2)
      #define  PROG_RESET        BIT(1)
      #define  FIFO_CLR          BIT(0)

   #define  hp_xfercnt_0         0x48
   #define  hp_xfercnt_1         0x49
   #define  hp_xfercnt_2         0x4A
   #define  hp_xfercnt_3         0x4B

   #define  hp_fifodata_0        0x4C
   #define  hp_fifodata_1        0x4D
   #define  hp_addstat           0x4E

      #define  SCAM_TIMER        BIT(7)
      #define  AUTO_RUNNING      BIT(6)
      #define  FAST_SYNC         BIT(5)
      #define  SCSI_MODE8        BIT(3)
      #define  SCSI_PAR_ERR      BIT(0)

   #define  hp_prgmcnt_0         0x4F

      #define  AUTO_PC_MASK      0x3F

   #define  hp_selfid_0          0x50
   #define  hp_selfid_1          0x51
   #define  hp_arb_id            0x52

      #define  ARB_ID            (BIT(3) + BIT(2) + BIT(1) + BIT(0))

   #define  hp_select_id         0x53

      #define  RESEL_ID          (BIT(7) + BIT(6) + BIT(5) + BIT(4))
      #define  SELECT_ID         (BIT(3) + BIT(2) + BIT(1) + BIT(0))

   #define  hp_synctarg_base     0x54
   #define  hp_synctarg_12       0x54
   #define  hp_synctarg_13       0x55
   #define  hp_synctarg_14       0x56
   #define  hp_synctarg_15       0x57

   #define  hp_synctarg_8        0x58
   #define  hp_synctarg_9        0x59
   #define  hp_synctarg_10       0x5A
   #define  hp_synctarg_11       0x5B

   #define  hp_synctarg_4        0x5C
   #define  hp_synctarg_5        0x5D
   #define  hp_synctarg_6        0x5E
   #define  hp_synctarg_7        0x5F

   #define  hp_synctarg_0        0x60
   #define  hp_synctarg_1        0x61
   #define  hp_synctarg_2        0x62
   #define  hp_synctarg_3        0x63

      #define  RATE_20MB         0x00
      #define  RATE_10MB         (              BIT(5))
      #define  RATE_6_6MB        (       BIT(6)       )   
      #define  RATE_5MB          (       BIT(6)+BIT(5))
      #define  RATE_4MB          (BIT(7)              )
      #define  RATE_3_33MB       (BIT(7)       +BIT(5))
      #define  RATE_2_85MB       (BIT(7)+BIT(6)       )
      #define  RATE_2_5MB        (BIT(7)+BIT(5)+BIT(6))
      #define  NEXT_CLK          BIT(5)
      #define  SLOWEST_SYNC      (BIT(7)+BIT(6)+BIT(5))
      #define  NARROW_SCSI       BIT(4)
      #define  SYNC_OFFSET       (BIT(3) + BIT(2) + BIT(1) + BIT(0))
      #define  DEFAULT_ASYNC     0x00
      #define  DEFAULT_OFFSET    0x0F

   #define  hp_autostart_0       0x64
   #define  hp_autostart_1       0x65
   #define  hp_autostart_2       0x66
   #define  hp_autostart_3       0x67



      #define  DISABLE  0x00
      #define  AUTO_IMMED    BIT(5)
      #define  SELECT   BIT(6)
      #define  RESELECT (BIT(6)+BIT(5))
      #define  BUSFREE  BIT(7)
      #define  XFER_0   (BIT(7)+BIT(5))
      #define  END_DATA (BIT(7)+BIT(6))
      #define  MSG_PHZ  (BIT(7)+BIT(6)+BIT(5))

   #define  hp_gp_reg_0          0x68
   #define  hp_gp_reg_1          0x69
   #define  hp_gp_reg_2          0x6A
   #define  hp_gp_reg_3          0x6B

   #define  hp_seltimeout        0x6C


      #define  TO_2ms            0x54      /* 2.0503ms */
      #define  TO_4ms            0x67      /* 3.9959ms */

      #define  TO_5ms            0x03      /* 4.9152ms */
      #define  TO_10ms           0x07      /* 11.xxxms */
      #define  TO_250ms          0x99      /* 250.68ms */
      #define  TO_290ms          0xB1      /* 289.99ms */
      #define  TO_350ms          0xD6      /* 350.62ms */
      #define  TO_417ms          0xFF      /* 417.79ms */

   #define  hp_clkctrl_0         0x6D

      #define  PWR_DWN           BIT(6)
      #define  ACTdeassert       BIT(4)
      #define  ATNonErr          BIT(3)
      #define  CLK_30MHZ         BIT(1)
      #define  CLK_40MHZ         (BIT(1) + BIT(0))
      #define  CLK_50MHZ         BIT(2)

      #define  CLKCTRL_DEFAULT   (ACTdeassert | CLK_40MHZ)

   #define  hp_fiforead          0x6E
   #define  hp_fifowrite         0x6F

   #define  hp_offsetctr         0x70
   #define  hp_xferstat          0x71

      #define  FIFO_FULL         BIT(7)
      #define  FIFO_EMPTY        BIT(6)
      #define  FIFO_MASK         0x3F   /* Mask for the FIFO count value. */
      #define  FIFO_LEN          0x20

   #define  hp_portctrl_1        0x72

      #define  EVEN_HOST_P       BIT(5)
      #define  INVT_SCSI         BIT(4)
      #define  CHK_SCSI_P        BIT(3)
      #define  HOST_MODE8        BIT(0)
      #define  HOST_MODE16       0x00

   #define  hp_xfer_pad          0x73

      #define  ID_UNLOCK         BIT(3)
      #define  XFER_PAD          BIT(2)

   #define  hp_scsidata_0        0x74
   #define  hp_scsidata_1        0x75
   #define  hp_timer_0           0x76
   #define  hp_timer_1           0x77

   #define  hp_reserved_78       0x78
   #define  hp_reserved_79       0x79
   #define  hp_reserved_7A       0x7A
   #define  hp_reserved_7B       0x7B

   #define  hp_reserved_7C       0x7C
   #define  hp_reserved_7D       0x7D
   #define  hp_reserved_7E       0x7E
   #define  hp_reserved_7F       0x7F

   #define  hp_aramBase          0x80
   #define  BIOS_DATA_OFFSET     0x60
   #define  BIOS_RELATIVE_CARD   0x64




      #define  AUTO_LEN 0x80
      #define  AR0      0x00
      #define  AR1      BITW(8)
      #define  AR2      BITW(9)
      #define  AR3      (BITW(9) + BITW(8))
      #define  SDATA    BITW(10)

      #define  NOP_OP   0x00        /* Nop command */

      #define  CRD_OP   BITW(11)     /* Cmp Reg. w/ Data */

      #define  CRR_OP   BITW(12)     /* Cmp Reg. w. Reg. */

      #define  CBE_OP   (BITW(14)+BITW(12)+BITW(11)) /* Cmp SCSI cmd class & Branch EQ */
      
      #define  CBN_OP   (BITW(14)+BITW(13))  /* Cmp SCSI cmd class & Branch NOT EQ */
      
      #define  CPE_OP   (BITW(14)+BITW(11))  /* Cmp SCSI phs & Branch EQ */

      #define  CPN_OP   (BITW(14)+BITW(12))  /* Cmp SCSI phs & Branch NOT EQ */


      #define  ADATA_OUT   0x00     
      #define  ADATA_IN    BITW(8)
      #define  ACOMMAND    BITW(10)
      #define  ASTATUS     (BITW(10)+BITW(8))
      #define  AMSG_OUT    (BITW(10)+BITW(9))
      #define  AMSG_IN     (BITW(10)+BITW(9)+BITW(8))
      #define  AILLEGAL    (BITW(9)+BITW(8))


      #define  BRH_OP   BITW(13)   /* Branch */

      
      #define  ALWAYS   0x00
      #define  EQUAL    BITW(8)
      #define  NOT_EQ   BITW(9)

      #define  TCB_OP   (BITW(13)+BITW(11))    /* Test condition & branch */

      
      #define  ATN_SET     BITW(8)
      #define  ATN_RESET   BITW(9)
      #define  XFER_CNT    (BITW(9)+BITW(8))
      #define  FIFO_0      BITW(10)
      #define  FIFO_NOT0   (BITW(10)+BITW(8))
      #define  T_USE_SYNC0 (BITW(10)+BITW(9))


      #define  MPM_OP   BITW(15)        /* Match phase and move data */

      #define  MDR_OP   (BITW(12)+BITW(11)) /* Move data to Reg. */

      #define  MRR_OP   BITW(14)        /* Move DReg. to Reg. */


      #define  S_IDREG  (BIT(2)+BIT(1)+BIT(0))


      #define  D_AR0    0x00
      #define  D_AR1    BIT(0)
      #define  D_AR2    BIT(1)
      #define  D_AR3    (BIT(1) + BIT(0))
      #define  D_SDATA  BIT(2)
      #define  D_BUCKET (BIT(2) + BIT(1) + BIT(0))


      #define  ADR_OP   (BITW(13)+BITW(12)) /* Logical AND Reg. w. Data */

      #define  ADS_OP   (BITW(14)+BITW(13)+BITW(12)) 

      #define  ODR_OP   (BITW(13)+BITW(12)+BITW(11))  

      #define  ODS_OP   (BITW(14)+BITW(13)+BITW(12)+BITW(11))  

      #define  STR_OP   (BITW(15)+BITW(14)) /* Store to A_Reg. */

      #define  AINT_ENA1   0x00
      #define  AINT_STAT1  BITW(8)
      #define  ASCSI_SIG   BITW(9)
      #define  ASCSI_CNTL  (BITW(9)+BITW(8))
      #define  APORT_CNTL  BITW(10)
      #define  ARST_CNTL   (BITW(10)+BITW(8))
      #define  AXFERCNT0   (BITW(10)+BITW(9))
      #define  AXFERCNT1   (BITW(10)+BITW(9)+BITW(8))
      #define  AXFERCNT2   BITW(11)
      #define  AFIFO_DATA  (BITW(11)+BITW(8))
      #define  ASCSISELID  (BITW(11)+BITW(9))
      #define  ASCSISYNC0  (BITW(11)+BITW(9)+BITW(8))


      #define  RAT_OP      (BITW(14)+BITW(13)+BITW(11))

      #define  SSI_OP      (BITW(15)+BITW(11))


      #define  SSI_ITAR_DISC	(ITAR_DISC >> 8)
      #define  SSI_IDO_STRT	(IDO_STRT >> 8)
      #define  SSI_IDI_STRT	(IDO_STRT >> 8)

      #define  SSI_ICMD_COMP	(ICMD_COMP >> 8)
      #define  SSI_ITICKLE	(ITICKLE >> 8)

      #define  SSI_IUNKWN	(IUNKWN >> 8)
      #define  SSI_INO_CC	(IUNKWN >> 8)
      #define  SSI_IRFAIL	(IUNKWN >> 8)


      #define  NP    0x10     /*Next Phase */
      #define  NTCMD 0x02     /*Non- Tagged Command start */
      #define  CMDPZ 0x04     /*Command phase */
      #define  DINT  0x12     /*Data Out/In interrupt */
      #define  DI    0x13     /*Data Out */
      #define  MI    0x14     /*Message In */
      #define  DC    0x19     /*Disconnect Message */
      #define  ST    0x1D     /*Status Phase */
      #define  UNKNWN 0x24    /*Unknown bus action */
      #define  CC    0x25     /*Command Completion failure */
      #define  TICK  0x26     /*New target reselected us. */
      #define  RFAIL 0x27     /*Reselection failed */
      #define  SELCHK 0x28     /*Select & Check SCSI ID latch reg */


      #define  ID_MSG_STRT    hp_aramBase + 0x00
      #define  NON_TAG_ID_MSG hp_aramBase + 0x06
      #define  CMD_STRT       hp_aramBase + 0x08
      #define  SYNC_MSGS      hp_aramBase + 0x08





      #define  TAG_STRT          0x00
      #define  SELECTION_START   0x00
      #define  DISCONNECT_START  0x10/2
      #define  END_DATA_START    0x14/2
      #define  NONTAG_STRT       0x02/2
      #define  CMD_ONLY_STRT     CMDPZ/2
      #define  TICKLE_STRT     TICK/2
      #define  SELCHK_STRT     SELCHK/2




#define mEEPROM_CLK_DELAY(port) (RD_HARPOON(port+hp_intstat_1))

#define mWAIT_10MS(port) (RD_HARPOON(port+hp_intstat_1))


#define CLR_XFER_CNT(port) (WR_HARPOON(port+hp_xfercnt_0, 0x00))

#define SET_XFER_CNT(port, data) (WR_HARP32(port,hp_xfercnt_0,data))

#define GET_XFER_CNT(port, xfercnt) {RD_HARP32(port,hp_xfercnt_0,xfercnt); xfercnt &= 0xFFFFFF;}
/* #define GET_XFER_CNT(port, xfercnt) (xfercnt = RD_HARPOON(port+hp_xfercnt_2), \
                                 xfercnt <<= 16,\
                                 xfercnt |= RDW_HARPOON((USHORT)(port+hp_xfercnt_0)))
 */
#if defined(DOS)
#define HP_SETUP_ADDR_CNT(port,addr,count) (WRW_HARPOON((USHORT)(port+hp_host_addr_lo), (USHORT)(addr & 0x0000FFFFL)),\
         addr >>= 16,\
         WRW_HARPOON((USHORT)(port+hp_host_addr_hmi), (USHORT)(addr & 0x0000FFFFL)),\
         WR_HARP32(port,hp_xfercnt_0,count),\
         WRW_HARPOON((USHORT)(port+hp_xfer_cnt_lo), (USHORT)(count & 0x0000FFFFL)),\
         count >>= 16,\
         WR_HARPOON(port+hp_xfer_cnt_hi, (count & 0xFF)))
#else
#define HP_SETUP_ADDR_CNT(port,addr,count) (WRW_HARPOON((port+hp_host_addr_lo), (USHORT)(addr & 0x0000FFFFL)),\
         addr >>= 16,\
         WRW_HARPOON((port+hp_host_addr_hmi), (USHORT)(addr & 0x0000FFFFL)),\
         WR_HARP32(port,hp_xfercnt_0,count),\
         WRW_HARPOON((port+hp_xfer_cnt_lo), (USHORT)(count & 0x0000FFFFL)),\
         count >>= 16,\
         WR_HARPOON(port+hp_xfer_cnt_hi, (count & 0xFF)))
#endif

#define ACCEPT_MSG(port) {while(RD_HARPOON(port+hp_scsisig) & SCSI_REQ){}\
                          WR_HARPOON(port+hp_scsisig, S_ILL_PH);}


#define ACCEPT_MSG_ATN(port) {while(RD_HARPOON(port+hp_scsisig) & SCSI_REQ){}\
                          WR_HARPOON(port+hp_scsisig, (S_ILL_PH|SCSI_ATN));}

#define ACCEPT_STAT(port) {while(RD_HARPOON(port+hp_scsisig) & SCSI_REQ){}\
                          WR_HARPOON(port+hp_scsisig, S_ILL_PH);}

#define ACCEPT_STAT_ATN(port) {while(RD_HARPOON(port+hp_scsisig) & SCSI_REQ){}\
                          WR_HARPOON(port+hp_scsisig, (S_ILL_PH|SCSI_ATN));}

#define DISABLE_AUTO(port) (WR_HARPOON(port+hp_scsireset, PROG_RESET),\
                        WR_HARPOON(port+hp_scsireset, 0x00))

#define ARAM_ACCESS(p_port) (WR_HARPOON(p_port+hp_page_ctrl, \
                             (RD_HARPOON(p_port+hp_page_ctrl) | SGRAM_ARAM)))

#define SGRAM_ACCESS(p_port) (WR_HARPOON(p_port+hp_page_ctrl, \
                             (RD_HARPOON(p_port+hp_page_ctrl) & ~SGRAM_ARAM)))

#define MDISABLE_INT(p_port) (WR_HARPOON(p_port+hp_page_ctrl, \
                             (RD_HARPOON(p_port+hp_page_ctrl) | G_INT_DISABLE)))

#define MENABLE_INT(p_port) (WR_HARPOON(p_port+hp_page_ctrl, \
                             (RD_HARPOON(