flashpoint.c

Linux内核源代码 为压缩文件 是<<Linux内核>>一书中的源代码

 *   $Revision: 1.4 $
 *
 *----------------------------------------------------------------------*/

#ifndef __EEPROM__
#define __EEPROM__

/*#include <globals.h>*/

#define  EEPROM_WD_CNT     256

#define  EEPROM_CHECK_SUM  0
#define  FW_SIGNATURE      2
#define  MODEL_NUMB_0      4
#define  MODEL_NUMB_1      5
#define  MODEL_NUMB_2      6
#define  MODEL_NUMB_3      7
#define  MODEL_NUMB_4      8
#define  MODEL_NUMB_5      9
#define  IO_BASE_ADDR      10
#define  IRQ_NUMBER        12
#define  PCI_INT_PIN       13
#define  BUS_DELAY         14       /*On time in byte 14 off delay in 15 */
#define  SYSTEM_CONFIG     16
#define  SCSI_CONFIG       17
#define  BIOS_CONFIG       18
#define  SPIN_UP_DELAY     19
#define  SCAM_CONFIG       20
#define  ADAPTER_SCSI_ID   24


#define  IGNORE_B_SCAN     32
#define  SEND_START_ENA    34
#define  DEVICE_ENABLE     36

#define  SYNC_RATE_TBL     38
#define  SYNC_RATE_TBL01   38
#define  SYNC_RATE_TBL23   40
#define  SYNC_RATE_TBL45   42
#define  SYNC_RATE_TBL67   44
#define  SYNC_RATE_TBL89   46
#define  SYNC_RATE_TBLab   48
#define  SYNC_RATE_TBLcd   50
#define  SYNC_RATE_TBLef   52



#define  EE_SCAMBASE      256 



   #define  DOM_MASTER     (BIT(0) + BIT(1))
   #define  SCAM_ENABLED   BIT(2)
   #define  SCAM_LEVEL2    BIT(3)


	#define	RENEGO_ENA		BITW(10)
	#define	CONNIO_ENA		BITW(11)
   #define  GREEN_PC_ENA   BITW(12)


   #define  AUTO_RATE_00   00
   #define  AUTO_RATE_05   01
   #define  AUTO_RATE_10   02
   #define  AUTO_RATE_20   03

   #define  WIDE_NEGO_BIT     BIT(7)
   #define  DISC_ENABLE_BIT   BIT(6)


#endif
/*----------------------------------------------------------------------
 *
 *
 *   Copyright 1995-1996 by Mylex Corporation.  All Rights Reserved
 *
 *   This file is available under both the GNU General Public License
 *   and a BSD-style copyright; see LICENSE.FlashPoint for details.
 *
 *   $Workfile:   harpoon.h  $
 *
 *   Description:  Register definitions for HARPOON ASIC.
 *
 *   $Date: 1997/07/09 21:44:36 $
 *
 *   $Revision: 1.9 $
 *
 *----------------------------------------------------------------------*/


/*#include <globals.h>*/

#ifndef __HARPOON__
#define __HARPOON__


   #define  hp_vendor_id_0       0x00		/* LSB */
      #define  ORION_VEND_0   0x4B
 
   #define  hp_vendor_id_1       0x01		/* MSB */
      #define  ORION_VEND_1   0x10

   #define  hp_device_id_0       0x02		/* LSB */
      #define  ORION_DEV_0    0x30 

   #define  hp_device_id_1       0x03		/* MSB */
      #define  ORION_DEV_1    0x81 

	/* Sub Vendor ID and Sub Device ID only available in
		Harpoon Version 2 and higher */

   #define  hp_sub_vendor_id_0   0x04		/* LSB */
   #define  hp_sub_vendor_id_1   0x05		/* MSB */
   #define  hp_sub_device_id_0   0x06		/* LSB */
   #define  hp_sub_device_id_1   0x07		/* MSB */


   #define  hp_dual_addr_lo      0x08
   #define  hp_dual_addr_lmi     0x09
   #define  hp_dual_addr_hmi     0x0A
   #define  hp_dual_addr_hi      0x0B

   #define  hp_semaphore         0x0C
      #define SCCB_MGR_ACTIVE    BIT(0)
      #define TICKLE_ME          BIT(1)
      #define SCCB_MGR_PRESENT   BIT(3)
      #define BIOS_IN_USE        BIT(4)

   #define  hp_user_defined_D    0x0D

   #define  hp_reserved_E        0x0E

   #define  hp_sys_ctrl          0x0F

      #define  STOP_CLK          BIT(0)      /*Turn off BusMaster Clock */
      #define  DRVR_RST          BIT(1)      /*Firmware Reset to 80C15 chip */
      #define  HALT_MACH         BIT(3)      /*Halt State Machine      */
      #define  HARD_ABORT        BIT(4)      /*Hard Abort              */
      #define  DIAG_MODE         BIT(5)      /*Diagnostic Mode         */

      #define  BM_ABORT_TMOUT    0x50        /*Halt State machine time out */

   #define  hp_sys_cfg           0x10

      #define  DONT_RST_FIFO     BIT(7)      /*Don't reset FIFO      */


   #define  hp_host_ctrl0        0x11

      #define  DUAL_ADDR_MODE    BIT(0)   /*Enable 64-bit addresses */
      #define  IO_MEM_SPACE      BIT(1)   /*I/O Memory Space    */
      #define  RESOURCE_LOCK     BIT(2)   /*Enable Resource Lock */
      #define  IGNOR_ACCESS_ERR  BIT(3)   /*Ignore Access Error */
      #define  HOST_INT_EDGE     BIT(4)   /*Host interrupt level/edge mode sel */
      #define  SIX_CLOCKS        BIT(5)   /*6 Clocks between Strobe   */
      #define  DMA_EVEN_PARITY   BIT(6)   /*Enable DMA Enen Parity */

/*
      #define  BURST_MODE        BIT(0)
*/

   #define  hp_reserved_12       0x12

   #define  hp_host_blk_cnt      0x13

      #define  XFER_BLK1         0x00     /*     0 0 0  1 byte per block*/
      #define  XFER_BLK2         0x01     /*     0 0 1  2 byte per block*/
      #define  XFER_BLK4         0x02     /*     0 1 0  4 byte per block*/
      #define  XFER_BLK8         0x03     /*     0 1 1  8 byte per block*/
      #define  XFER_BLK16        0x04     /*     1 0 0 16 byte per block*/
      #define  XFER_BLK32        0x05     /*     1 0 1 32 byte per block*/
      #define  XFER_BLK64        0x06     /*     1 1 0 64 byte per block*/
   
      #define  BM_THRESHOLD      0x40     /* PCI mode can only xfer 16 bytes*/


   #define  hp_reserved_14       0x14
   #define  hp_reserved_15       0x15
   #define  hp_reserved_16       0x16

   #define  hp_int_mask          0x17

      #define  INT_CMD_COMPL     BIT(0)   /* DMA command complete   */
      #define  INT_EXT_STATUS    BIT(1)   /* Extended Status Set    */
      #define  INT_SCSI          BIT(2)   /* Scsi block interrupt   */
      #define  INT_FIFO_RDY      BIT(4)   /* FIFO data ready        */


   #define  hp_xfer_cnt_lo       0x18
   #define  hp_xfer_cnt_mi       0x19
   #define  hp_xfer_cnt_hi       0x1A
   #define  hp_xfer_cmd          0x1B

      #define  XFER_HOST_DMA     0x00     /*     0 0 0 Transfer Host -> DMA */
      #define  XFER_DMA_HOST     0x01     /*     0 0 1 Transfer DMA  -> Host */
      #define  XFER_HOST_MPU     0x02     /*     0 1 0 Transfer Host -> MPU  */
      #define  XFER_MPU_HOST     0x03     /*     0 1 1 Transfer MPU  -> Host */
      #define  XFER_DMA_MPU      0x04     /*     1 0 0 Transfer DMA  -> MPU  */
      #define  XFER_MPU_DMA      0x05     /*     1 0 1 Transfer MPU  -> DMA  */
      #define  SET_SEMAPHORE     0x06     /*     1 1 0 Set Semaphore         */
      #define  XFER_NOP          0x07     /*     1 1 1 Transfer NOP          */
      #define  XFER_MB_MPU       0x06     /*     1 1 0 Transfer MB -> MPU */
      #define  XFER_MB_DMA       0x07     /*     1 1 1 Transfer MB -> DMA */


      #define  XFER_HOST_AUTO    0x00     /*     0 0 Auto Transfer Size   */
      #define  XFER_HOST_8BIT    0x08     /*     0 1 8 BIT Transfer Size  */
      #define  XFER_HOST_16BIT   0x10     /*     1 0 16 BIT Transfer Size */
      #define  XFER_HOST_32BIT   0x18     /*     1 1 32 BIT Transfer Size */

      #define  XFER_DMA_8BIT     0x20     /*     0 1 8 BIT  Transfer Size */
      #define  XFER_DMA_16BIT    0x40     /*     1 0 16 BIT Transfer Size */

      #define  DISABLE_INT       BIT(7)   /*Do not interrupt at end of cmd. */

      #define  HOST_WRT_CMD      ((DISABLE_INT + XFER_HOST_DMA + XFER_HOST_AUTO + XFER_DMA_8BIT))
      #define  HOST_RD_CMD       ((DISABLE_INT + XFER_DMA_HOST + XFER_HOST_AUTO + XFER_DMA_8BIT))
      #define  WIDE_HOST_WRT_CMD ((DISABLE_INT + XFER_HOST_DMA + XFER_HOST_AUTO + XFER_DMA_16BIT))
      #define  WIDE_HOST_RD_CMD  ((DISABLE_INT + XFER_DMA_HOST + XFER_HOST_AUTO + XFER_DMA_16BIT))

   #define  hp_host_addr_lo      0x1C
   #define  hp_host_addr_lmi     0x1D
   #define  hp_host_addr_hmi     0x1E
   #define  hp_host_addr_hi      0x1F

   #define  hp_pio_data          0x20
   #define  hp_reserved_21       0x21
   #define  hp_ee_ctrl           0x22

      #define  EXT_ARB_ACK       BIT(7)
      #define  SCSI_TERM_ENA_H   BIT(6)   /* SCSI high byte terminator */
      #define  SEE_MS            BIT(5)
      #define  SEE_CS            BIT(3)
      #define  SEE_CLK           BIT(2)
      #define  SEE_DO            BIT(1)
      #define  SEE_DI            BIT(0)

      #define  EE_READ           0x06
      #define  EE_WRITE          0x05
      #define  EWEN              0x04
      #define  EWEN_ADDR         0x03C0
      #define  EWDS              0x04
      #define  EWDS_ADDR         0x0000

   #define  hp_brdctl            0x23

      #define  DAT_7             BIT(7)
      #define  DAT_6             BIT(6)
      #define  DAT_5             BIT(5)
      #define  BRD_STB           BIT(4)
      #define  BRD_CS            BIT(3)
      #define  BRD_WR            BIT(2)

   #define  hp_reserved_24       0x24
   #define  hp_reserved_25       0x25




   #define  hp_bm_ctrl           0x26

      #define  SCSI_TERM_ENA_L   BIT(0)   /*Enable/Disable external terminators */
      #define  FLUSH_XFER_CNTR   BIT(1)   /*Flush transfer counter */
      #define  BM_XFER_MIN_8     BIT(2)   /*Enable bus master transfer of 9 */
      #define  BIOS_ENA          BIT(3)   /*Enable BIOS/FLASH Enable */
      #define  FORCE1_XFER       BIT(5)   /*Always xfer one byte in byte mode */
      #define  FAST_SINGLE       BIT(6)   /*?? */

      #define  BMCTRL_DEFAULT    (FORCE1_XFER|FAST_SINGLE|SCSI_TERM_ENA_L)

   #define  hp_reserved_27       0x27

   #define  hp_sg_addr           0x28
   #define  hp_page_ctrl         0x29

      #define  SCATTER_EN        BIT(0)   
      #define  SGRAM_ARAM        BIT(1)   
      #define  BIOS_SHADOW       BIT(2)   
      #define  G_INT_DISABLE     BIT(3)   /* Enable/Disable all Interrupts */
      #define  NARROW_SCSI_CARD  BIT(4)   /* NARROW/WIDE SCSI config pin */

   #define  hp_reserved_2A       0x2A
   #define  hp_pci_cmd_cfg       0x2B

      #define  IO_SPACE_ENA      BIT(0)   /*enable I/O space */
      #define  MEM_SPACE_ENA     BIT(1)   /*enable memory space */
      #define  BUS_MSTR_ENA      BIT(2)   /*enable bus master operation */
      #define  MEM_WI_ENA        BIT(4)   /*enable Write and Invalidate */
      #define  PAR_ERR_RESP      BIT(6)   /*enable parity error responce. */

   #define  hp_reserved_2C       0x2C

   #define  hp_pci_stat_cfg      0x2D

      #define  DATA_PARITY_ERR   BIT(0)   
      #define  REC_TARGET_ABORT  BIT(4)   /*received Target abort */
      #define  REC_MASTER_ABORT  BIT(5)   /*received Master abort */
      #define  SIG_SYSTEM_ERR    BIT(6)   
      #define  DETECTED_PAR_ERR  BIT(7)   

   #define  hp_reserved_2E       0x2E

   #define  hp_sys_status        0x2F

      #define  SLV_DATA_RDY      BIT(0)   /*Slave data ready */
      #define  XFER_CNT_ZERO     BIT(1)   /*Transfer counter = 0 */
      #define  BM_FIFO_EMPTY     BIT(2)   /*FIFO empty */
      #define  BM_FIFO_FULL      BIT(3)   /*FIFO full */
      #define  HOST_OP_DONE      BIT(4)   /*host operation done */
      #define  DMA_OP_DONE       BIT(5)   /*DMA operation done */
      #define  SLV_OP_DONE       BIT(6)   /*Slave operation done */
      #define  PWR_ON_FLAG       BIT(7)   /*Power on flag */

   #define  hp_reserved_30       0x30

   #define  hp_host_status0      0x31

      #define  HOST_TERM         BIT(5)   /*Host Terminal Count */
      #define  HOST_TRSHLD       BIT(6)   /*Host Threshold      */
      #define  CONNECTED_2_HOST  BIT(7)   /*Connected to Host   */

   #define  hp_reserved_32       0x32

   #define  hp_rev_num           0x33

      #define  REV_A_CONST       0x0E
      #define  REV_B_CONST       0x0E

   #define  hp_stack_data        0x34
   #define  hp_stack_addr        0x35

   #define  hp_ext_status        0x36

      #define  BM_FORCE_OFF      BIT(0)   /*Bus Master is forced to get off */
      #define  PCI_TGT_ABORT     BIT(0)   /*PCI bus master transaction aborted */
      #define  PCI_DEV_TMOUT     BIT(1)   /*PCI Device Time out */
      #define  FIFO_TC_NOT_ZERO  BIT(2)   /*FIFO or transfer counter not zero */
      #define  CHIP_RST_OCCUR    BIT(3)   /*Chip reset occurs */
      #define  CMD_ABORTED       BIT(4)   /*Command aborted */
      #define  BM_PARITY_ERR     BIT(5)   /*parity error on data received   */
      #define  PIO_OVERRUN       BIT(6)   /*Slave data overrun */
      #define  BM_CMD_BUSY       BIT(7)   /*Bus master transfer command busy */
      #define  BAD_EXT_STATUS    (BM_FORCE_OFF | PCI_DEV_TMOUT | CMD_ABORTED | \
                                  BM_PARITY_ERR | PIO_OVERRUN)

   #define  hp_int_status        0x37
      
      #define  BM_CMD_CMPL       BIT(0)   /*Bus Master command complete */
      #define  EXT_STATUS_ON     BIT(1)   /*Extended status is valid */
      #define  SCSI_INTERRUPT    BIT(2)   /*Global indication of a SCSI int. */
      #define  BM_FIFO_RDY       BIT(4)   
      #define  INT_ASSERTED      BIT(5)   /* */
      #define  SRAM_BUSY         BIT(6)   /*Scatter/Gather RAM busy */
      #define  CMD_REG_BUSY      BIT(7)                                       


   #define  hp_fifo_cnt          0x38
   #define  hp_curr_host_cnt     0x39
   #define  hp_reserved_3A       0x3A
   #define  hp_fifo_in_addr      0x3B

   #define  hp_fifo_out_addr     0x3C
   #define  hp_reserved_3D       0x3D
   #define  hp_reserved_3E       0x3E
   #define  hp_reserved_3F       0x3F



   extern USHORT default_intena;

   #define  hp_intena		 0x40

      #define  RESET		 BITW(7)
      #define  PROG_HLT		 BITW(6)  
      #define  PARITY		 BITW(5)
      #define  FIFO		 BITW(4)
      #define  SEL		 BITW(3)
      #define  SCAM_SEL		 BITW(2) 
      #define  RSEL		 BITW(1)
      #define  TIMEOUT		 BITW(0)
      #define  BUS_FREE		 BITW(15)
      #define  XFER_CNT_0	 BITW(14)
      #define  PHASE		 BITW(13)
      #define  IUNKWN		 BITW(12)
      #define  ICMD_COMP	 BITW(11)
      #define  ITICKLE		 BITW(10)
      #define  IDO_STRT		 BITW(9)
      #define  ITAR_DISC	 BITW(8)
      #define  AUTO_INT		 (BITW(12)+BITW(11)+BITW(10)+BITW(9)+BITW(8))
      #define  CLR_ALL_INT	 0xFFFF
      #define  CLR_ALL_INT_1	 0xFF00

   #define  hp_intstat		 0x42

   #define  hp_scsisig           0x44

      #define  SCSI_SEL          BIT(7)
      #define  SCSI_BSY          BIT(6)
      #define  SCSI_REQ          BIT(5)
      #define  SCSI_ACK          BIT(4)
      #define  SCSI_ATN          BIT(3)
      #define  SCSI_CD           BIT(2)
      #define  SCSI_MSG          BIT(1)
      #define  SCSI_IOBIT        BIT(0)