📄 qlogicfas.c
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/*----------------------------------------------------------------*//* Qlogic linux driver - work in progress. No Warranty express or implied. Use at your own risk. Support Tort Reform so you won't have to read all these silly disclaimers. Copyright 1994, Tom Zerucha. tz@execpc.com Additional Code, and much appreciated help by Michael A. Griffith grif@cs.ucr.edu Thanks to Eric Youngdale and Dave Hinds for loadable module and PCMCIA help respectively, and for suffering through my foolishness during the debugging process. Reference Qlogic FAS408 Technical Manual, 53408-510-00A, May 10, 1994 (you can reference it, but it is incomplete and inaccurate in places) Version 0.46 1/30/97 - kernel 1.2.0+ Functions as standalone, loadable, and PCMCIA driver, the latter from Dave Hinds' PCMCIA package. Redistributable under terms of the GNU Public License*//*----------------------------------------------------------------*//* Configuration *//* Set the following to 2 to use normal interrupt (active high/totempole- tristate), otherwise use 0 (REQUIRED FOR PCMCIA) for active low, open drain */#define QL_INT_ACTIVE_HIGH 2/* Set the following to 1 to enable the use of interrupts. Note that 0 tends to be more stable, but slower (or ties up the system more) */#define QL_USE_IRQ 1/* Set the following to max out the speed of the PIO PseudoDMA transfers, again, 0 tends to be slower, but more stable. */#define QL_TURBO_PDMA 1/* This should be 1 to enable parity detection */#define QL_ENABLE_PARITY 1/* This will reset all devices when the driver is initialized (during bootup). The other linux drivers don't do this, but the DOS drivers do, and after using DOS or some kind of crash or lockup this will bring things back without requiring a cold boot. It does take some time to recover from a reset, so it is slower, and I have seen timeouts so that devices weren't recognized when this was set. */#define QL_RESET_AT_START 0/* crystal frequency in megahertz (for offset 5 and 9) Please set this for your card. Most Qlogic cards are 40 Mhz. The Control Concepts ISA (not VLB) is 24 Mhz */#define XTALFREQ 40/**********//* DANGER! modify these at your own risk *//* SLOWCABLE can usually be reset to zero if you have a clean setup and proper termination. The rest are for synchronous transfers and other advanced features if your device can transfer faster than 5Mb/sec. If you are really curious, email me for a quick howto until I have something official *//**********//*****//* config register 1 (offset 8) options *//* This needs to be set to 1 if your cabling is long or noisy */#define SLOWCABLE 1/*****//* offset 0xc *//* This will set fast (10Mhz) synchronous timing when set to 1 For this to have an effect, FASTCLK must also be 1 */#define FASTSCSI 0/* This when set to 1 will set a faster sync transfer rate */#define FASTCLK 0/*(XTALFREQ>25?1:0)*//*****//* offset 6 *//* This is the sync transfer divisor, XTALFREQ/X will be the maximum achievable data rate (assuming the rest of the system is capable and set properly) */#define SYNCXFRPD 5/*(XTALFREQ/5)*//*****//* offset 7 *//* This is the count of how many synchronous transfers can take place i.e. how many reqs can occur before an ack is given. The maximum value for this is 15, the upper bits can modify REQ/ACK assertion and deassertion during synchronous transfers If this is 0, the bus will only transfer asynchronously */#define SYNCOFFST 0/* for the curious, bits 7&6 control the deassertion delay in 1/2 cycles of the 40Mhz clock. If FASTCLK is 1, specifying 01 (1/2) will cause the deassertion to be early by 1/2 clock. Bits 5&4 control the assertion delay, also in 1/2 clocks (FASTCLK is ignored here). *//*----------------------------------------------------------------*/#ifdef PCMCIA#undef QL_INT_ACTIVE_HIGH#define QL_INT_ACTIVE_HIGH 0#endif #include <linux/module.h>#ifdef PCMCIA#undef MODULE#endif #include <linux/blk.h> /* to get disk capacity */#include <linux/kernel.h>#include <linux/string.h>#include <linux/ioport.h>#include <linux/sched.h>#include <linux/proc_fs.h>#include <linux/unistd.h>#include <linux/spinlock.h>#include <asm/io.h>#include <asm/irq.h>#include "sd.h"#include "hosts.h"#include "qlogicfas.h"#include<linux/stat.h>/*----------------------------------------------------------------*//* driver state info, local to driver */static int qbase = 0; /* Port */static int qinitid; /* initiator ID */static int qabort; /* Flag to cause an abort */static int qlirq = -1; /* IRQ being used */static char qinfo[80]; /* description */static Scsi_Cmnd *qlcmd; /* current command being processed */static int qlcfg5 = ( XTALFREQ << 5 ); /* 15625/512 */static int qlcfg6 = SYNCXFRPD;static int qlcfg7 = SYNCOFFST;static int qlcfg8 = ( SLOWCABLE << 7 ) | ( QL_ENABLE_PARITY << 4 );static int qlcfg9 = ( ( XTALFREQ + 4 ) / 5 );static int qlcfgc = ( FASTCLK << 3 ) | ( FASTSCSI << 4 );/*----------------------------------------------------------------*//* The qlogic card uses two register maps - These macros select which one */#define REG0 ( outb( inb( qbase + 0xd ) & 0x7f , qbase + 0xd ), outb( 4 , qbase + 0xd ))#define REG1 ( outb( inb( qbase + 0xd ) | 0x80 , qbase + 0xd ), outb( 0xb4 | QL_INT_ACTIVE_HIGH , qbase + 0xd ))/* following is watchdog timeout in microseconds */#define WATCHDOG 5000000/*----------------------------------------------------------------*//* the following will set the monitor border color (useful to find where something crashed or gets stuck at and as a simple profiler) */#if 0#define rtrc(i) {inb(0x3da);outb(0x31,0x3c0);outb((i),0x3c0);}#else#define rtrc(i) {}#endif/*----------------------------------------------------------------*//* local functions *//*----------------------------------------------------------------*/static void ql_zap(void);/* error recovery - reset everything */void ql_zap(){int x;unsigned long flags; save_flags( flags ); cli(); x = inb(qbase + 0xd); REG0; outb(3, qbase + 3); /* reset SCSI */ outb(2, qbase + 3); /* reset chip */ if (x & 0x80) REG1; restore_flags( flags );}/*----------------------------------------------------------------*//* do pseudo-dma */static int ql_pdma(int phase, char *request, int reqlen){int j; j = 0; if (phase & 1) { /* in */#if QL_TURBO_PDMArtrc(4) /* empty fifo in large chunks */ if( reqlen >= 128 && (inb( qbase + 8 ) & 2) ) { /* full */ insl( qbase + 4, request, 32 ); reqlen -= 128; request += 128; } while( reqlen >= 84 && !( j & 0xc0 ) ) /* 2/3 */ if( (j=inb( qbase + 8 )) & 4 ) { insl( qbase + 4, request, 21 ); reqlen -= 84; request += 84; } if( reqlen >= 44 && (inb( qbase + 8 ) & 8) ) { /* 1/3 */ insl( qbase + 4, request, 11 ); reqlen -= 44; request += 44; }#endif /* until both empty and int (or until reclen is 0) */rtrc(7) j = 0; while( reqlen && !( (j & 0x10) && (j & 0xc0) ) ) { /* while bytes to receive and not empty */ j &= 0xc0; while ( reqlen && !( (j=inb(qbase + 8)) & 0x10 ) ) { *request++ = inb(qbase + 4); reqlen--; } if( j & 0x10 ) j = inb(qbase+8); } } else { /* out */#if QL_TURBO_PDMArtrc(4) if( reqlen >= 128 && inb( qbase + 8 ) & 0x10 ) { /* empty */ outsl(qbase + 4, request, 32 ); reqlen -= 128; request += 128; } while( reqlen >= 84 && !( j & 0xc0 ) ) /* 1/3 */ if( !((j=inb( qbase + 8 )) & 8) ) { outsl( qbase + 4, request, 21 ); reqlen -= 84; request += 84; } if( reqlen >= 40 && !(inb( qbase + 8 ) & 4 ) ) { /* 2/3 */ outsl( qbase + 4, request, 10 ); reqlen -= 40; request += 40; }#endif /* until full and int (or until reclen is 0) */rtrc(7) j = 0; while( reqlen && !( (j & 2) && (j & 0xc0) ) ) { /* while bytes to send and not full */ while ( reqlen && !( (j=inb(qbase + 8)) & 2 ) ) { outb(*request++, qbase + 4); reqlen--; } if( j & 2 ) j = inb(qbase+8); } }/* maybe return reqlen */ return inb( qbase + 8 ) & 0xc0;}/*----------------------------------------------------------------*//* wait for interrupt flag (polled - not real hardware interrupt) */static int ql_wai(void){int i,k; k = 0; i = jiffies + WATCHDOG; while ( i > jiffies && !qabort && !((k = inb(qbase + 4)) & 0xe0)) barrier(); if (i <= jiffies) return (DID_TIME_OUT); if (qabort) return (qabort == 1 ? DID_ABORT : DID_RESET); if (k & 0x60) ql_zap(); if (k & 0x20) return (DID_PARITY); if (k & 0x40) return (DID_ERROR); return 0;}/*----------------------------------------------------------------*//* initiate scsi command - queueing handler */static void ql_icmd(Scsi_Cmnd * cmd){unsigned int i;unsigned long flags; qabort = 0; save_flags( flags ); cli(); REG0;/* clearing of interrupts and the fifo is needed */ inb(qbase + 5); /* clear interrupts */ if (inb(qbase + 5)) /* if still interrupting */ outb(2, qbase + 3); /* reset chip */ else if (inb(qbase + 7) & 0x1f) outb(1, qbase + 3); /* clear fifo */ while (inb(qbase + 5)); /* clear ints */ REG1; outb(1, qbase + 8); /* set for PIO pseudo DMA */ outb(0, qbase + 0xb); /* disable ints */ inb(qbase + 8); /* clear int bits */ REG0; outb(0x40, qbase + 0xb); /* enable features *//* configurables */ outb( qlcfgc , qbase + 0xc);/* config: no reset interrupt, (initiator) bus id */ outb( 0x40 | qlcfg8 | qinitid, qbase + 8); outb( qlcfg7 , qbase + 7 ); outb( qlcfg6 , qbase + 6 );/**/ outb(qlcfg5, qbase + 5); /* select timer */ outb(qlcfg9 & 7, qbase + 9); /* prescaler *//* outb(0x99, qbase + 5); */ outb(cmd->target, qbase + 4); for (i = 0; i < cmd->cmd_len; i++) outb(cmd->cmnd[i], qbase + 2); qlcmd = cmd; outb(0x41, qbase + 3); /* select and send command */ restore_flags( flags );}/*----------------------------------------------------------------*//* process scsi command - usually after interrupt */static unsigned int ql_pcmd(Scsi_Cmnd * cmd){unsigned int i, j, k;unsigned int result; /* ultimate return result */unsigned int status; /* scsi returned status */unsigned int message; /* scsi returned message */unsigned int phase; /* recorded scsi phase */unsigned int reqlen; /* total length of transfer */struct scatterlist *sglist; /* scatter-gather list pointer */
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