ncr53c9x.h

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/* NCR53C9x.c:  Defines and structures for the NCR53C9x generic driver.
 *
 * Originaly esp.h:  Defines and structures for the Sparc ESP 
 *                   (Enhanced SCSI Processor) driver under Linux.
 *
 * Copyright (C) 1995 David S. Miller ([e-mail])
 *
 * Generalization by Jesper Skov ([e-mail])
 *
 * More generalization (for i386 stuff) by Tymm Twillman ([e-mail])
 */

#ifndef NCR53C9X_H
#define NCR53C9X_H

#include <linux/config.h>

/* djweis for mac driver */
#if defined(CONFIG_MAC)
#define PAD_SIZE 15
#else
#define PAD_SIZE 3
#endif

/* Handle multiple hostadapters on Amiga
 * generally PAD_SIZE = 3
 * but there is one exception: Oktagon (PAD_SIZE = 1) */
#if defined(CONFIG_OKTAGON_SCSI) || defined(CONFIG_OKTAGON_SCSI_MODULE)
#undef PAD_SIZE
#if defined(CONFIG_BLZ1230_SCSI) || defined(CONFIG_BLZ1230_SCSI_MODULE) || \
    defined(CONFIG_BLZ2060_SCSI) || defined(CONFIG_BLZ2060_SCSI_MODULE) || \
    defined(CONFIG_CYBERSTORM_SCSI) || defined(CONFIG_CYBERSTORM_SCSI_MODULE) || \
    defined(CONFIG_CYBERSTORMII_SCSI) || defined(CONFIG_CYBERSTORMII_SCSI_MODULE) || \
    defined(CONFIG_FASTLANE_SCSI) || defined(CONFIG_FASTLANE_SCSI_MODULE)
#define MULTIPLE_PAD_SIZES
#else
#define PAD_SIZE 1
#endif
#endif

/* Macros for debugging messages */

#define DEBUG_ESP
/* #define DEBUG_ESP_DATA */
/* #define DEBUG_ESP_QUEUE */
/* #define DEBUG_ESP_DISCONNECT */
/* #define DEBUG_ESP_STATUS */
/* #define DEBUG_ESP_PHASES */
/* #define DEBUG_ESP_WORKBUS */
/* #define DEBUG_STATE_MACHINE */
/* #define DEBUG_ESP_CMDS */
/* #define DEBUG_ESP_IRQS */
/* #define DEBUG_SDTR */
/* #define DEBUG_ESP_SG */

/* Use the following to sprinkle debugging messages in a way which
 * suits you if combinations of the above become too verbose when
 * trying to track down a specific problem.
 */
/* #define DEBUG_ESP_MISC */

#if defined(DEBUG_ESP)
#define ESPLOG(foo)  printk foo
#else
#define ESPLOG(foo)
#endif /* (DEBUG_ESP) */

#if defined(DEBUG_ESP_DATA)
#define ESPDATA(foo)  printk foo
#else
#define ESPDATA(foo)
#endif

#if defined(DEBUG_ESP_QUEUE)
#define ESPQUEUE(foo)  printk foo
#else
#define ESPQUEUE(foo)
#endif

#if defined(DEBUG_ESP_DISCONNECT)
#define ESPDISC(foo)  printk foo
#else
#define ESPDISC(foo)
#endif

#if defined(DEBUG_ESP_STATUS)
#define ESPSTAT(foo)  printk foo
#else
#define ESPSTAT(foo)
#endif

#if defined(DEBUG_ESP_PHASES)
#define ESPPHASE(foo)  printk foo
#else
#define ESPPHASE(foo)
#endif

#if defined(DEBUG_ESP_WORKBUS)
#define ESPBUS(foo)  printk foo
#else
#define ESPBUS(foo)
#endif

#if defined(DEBUG_ESP_IRQS)
#define ESPIRQ(foo)  printk foo
#else
#define ESPIRQ(foo)
#endif

#if defined(DEBUG_SDTR)
#define ESPSDTR(foo)  printk foo
#else
#define ESPSDTR(foo)
#endif

#if defined(DEBUG_ESP_MISC)
#define ESPMISC(foo)  printk foo
#else
#define ESPMISC(foo)
#endif

/*
 * padding for register structure
 */
#ifdef CONFIG_JAZZ_ESP
#define EREGS_PAD(n)
#else
#ifndef MULTIPLE_PAD_SIZES
#define EREGS_PAD(n)    unchar n[PAD_SIZE];
#endif
#endif

/* The ESP SCSI controllers have their register sets in three
 * "classes":
 *
 * 1) Registers which are both read and write.
 * 2) Registers which are read only.
 * 3) Registers which are write only.
 *
 * Yet, they all live within the same IO space.
 */

#ifndef __i386__

#ifndef MULTIPLE_PAD_SIZES

#ifdef CONFIG_CPU_HAS_WB
#include <asm/wbflush.h>
#define esp_write(__reg, __val) do{(__reg) = (__val); wbflush();} while(0)
#else
#define esp_write(__reg, __val) ((__reg) = (__val))
#endif
#define esp_read(__reg) (__reg)

struct ESP_regs {
                                /* Access    Description              Offset */
    volatile unchar esp_tclow;  /* rw  Low bits of the transfer count 0x00   */
                                EREGS_PAD(tlpad1);
    volatile unchar esp_tcmed;  /* rw  Mid bits of the transfer count 0x04   */
                                EREGS_PAD(fdpad);
    volatile unchar esp_fdata;  /* rw  FIFO data bits                 0x08   */
                                EREGS_PAD(cbpad);
    volatile unchar esp_cmnd;   /* rw  SCSI command bits              0x0c   */
                                EREGS_PAD(stpad);
    volatile unchar esp_status; /* ro  ESP status register            0x10   */
#define esp_busid   esp_status  /* wo  Bus ID for select/reselect     0x10   */
                                EREGS_PAD(irqpd);
    volatile unchar esp_intrpt; /* ro  Kind of interrupt              0x14   */
#define esp_timeo   esp_intrpt  /* wo  Timeout value for select/resel 0x14   */
                                EREGS_PAD(sspad);
    volatile unchar esp_sstep;  /* ro  Sequence step register         0x18   */
#define esp_stp     esp_sstep   /* wo  Transfer period per sync       0x18   */
                                EREGS_PAD(ffpad);
    volatile unchar esp_fflags; /* ro  Bits of current FIFO info      0x1c   */
#define esp_soff    esp_fflags  /* wo  Sync offset                    0x1c   */
                                EREGS_PAD(cf1pd);
    volatile unchar esp_cfg1;   /* rw  First configuration register   0x20   */
                                EREGS_PAD(cfpad);
    volatile unchar esp_cfact;  /* wo  Clock conversion factor        0x24   */
                                EREGS_PAD(ctpad);
    volatile unchar esp_ctest;  /* wo  Chip test register             0x28   */
                                EREGS_PAD(cf2pd);
    volatile unchar esp_cfg2;   /* rw  Second configuration register  0x2c   */
                                EREGS_PAD(cf3pd);

    /* The following is only found on the 53C9X series SCSI chips */
    volatile unchar esp_cfg3;   /* rw  Third configuration register   0x30  */
                                EREGS_PAD(cf4pd);
    volatile unchar esp_cfg4;   /* rw  Fourth configuration register  0x34  */
                                EREGS_PAD(thpd);
    /* The following is found on all chips except the NCR53C90 (ESP100) */
    volatile unchar esp_tchi;   /* rw  High bits of transfer count    0x38  */
#define esp_uid     esp_tchi    /* ro  Unique ID code                 0x38  */
                                EREGS_PAD(fgpad);    
    volatile unchar esp_fgrnd;  /* rw  Data base for fifo             0x3c  */
};

#else /* MULTIPLE_PAD_SIZES */

#define esp_write(__reg, __val) (*(__reg) = (__val))
#define esp_read(__reg) (*(__reg))

struct ESP_regs {
    unsigned char io_addr[64]; /* dummy */
                                                 /* Access    Description              Offset */
#define esp_tclow   io_addr                      /* rw  Low bits of the transfer count 0x00   */
#define esp_tcmed   io_addr + (1<<(esp->shift))  /* rw  Mid bits of the transfer count 0x04   */
#define esp_fdata   io_addr + (2<<(esp->shift))  /* rw  FIFO data bits                 0x08   */
#define esp_cmnd    io_addr + (3<<(esp->shift))  /* rw  SCSI command bits              0x0c   */
#define esp_status  io_addr + (4<<(esp->shift))  /* ro  ESP status register            0x10   */
#define esp_busid   esp_status                   /* wo  Bus ID for select/reselect     0x10   */
#define esp_intrpt  io_addr + (5<<(esp->shift))  /* ro  Kind of interrupt              0x14   */
#define esp_timeo   esp_intrpt                   /* wo  Timeout value for select/resel 0x14   */
#define esp_sstep   io_addr + (6<<(esp->shift))  /* ro  Sequence step register         0x18   */
#define esp_stp     esp_sstep                    /* wo  Transfer period per sync       0x18   */
#define esp_fflags  io_addr + (7<<(esp->shift))  /* ro  Bits of current FIFO info      0x1c   */
#define esp_soff    esp_fflags                   /* wo  Sync offset                    0x1c   */
#define esp_cfg1    io_addr + (8<<(esp->shift))  /* rw  First configuration register   0x20   */
#define esp_cfact   io_addr + (9<<(esp->shift))  /* wo  Clock conversion factor        0x24   */
#define esp_ctest   io_addr + (10<<(esp->shift)) /* wo  Chip test register             0x28   */
#define esp_cfg2    io_addr + (11<<(esp->shift)) /* rw  Second configuration register  0x2c   */

    /* The following is only found on the 53C9X series SCSI chips */
#define esp_cfg3    io_addr + (12<<(esp->shift)) /* rw  Third configuration register   0x30  */
#define esp_cfg4    io_addr + (13<<(esp->shift)) /* rw  Fourth configuration register  0x34  */

    /* The following is found on all chips except the NCR53C90 (ESP100) */
#define esp_tchi    io_addr + (14<<(esp->shift)) /* rw  High bits of transfer count    0x38  */
#define esp_uid     esp_tchi                     /* ro  Unique ID code                 0x38  */
#define esp_fgrnd   io_addr + (15<<(esp->shift)) /* rw  Data base for fifo             0x3c  */
};

#endif

#else /* !defined __i386__ */

#define esp_write(__reg, __val) outb((__val), (__reg))
#define esp_read(__reg) inb((__reg))

struct ESP_regs {
    unsigned int io_addr;
                                 /* Access    Description              Offset */
#define esp_tclow   io_addr      /* rw  Low bits of the transfer count 0x00   */
#define esp_tcmed   io_addr + 1  /* rw  Mid bits of the transfer count 0x04   */
#define esp_fdata   io_addr + 2  /* rw  FIFO data bits                 0x08   */
#define esp_cmnd    io_addr + 3  /* rw  SCSI command bits              0x0c   */
#define esp_status  io_addr + 4  /* ro  ESP status register            0x10   */
#define esp_busid   esp_status   /* wo  Bus ID for select/reselect     0x10   */
#define esp_intrpt  io_addr + 5  /* ro  Kind of interrupt              0x14   */
#define esp_timeo   esp_intrpt   /* wo  Timeout value for select/resel 0x14   */
#define esp_sstep   io_addr + 6  /* ro  Sequence step register         0x18   */
#define esp_stp     esp_sstep    /* wo  Transfer period per sync       0x18   */
#define esp_fflags  io_addr + 7  /* ro  Bits of current FIFO info      0x1c   */
#define esp_soff    esp_fflags   /* wo  Sync offset                    0x1c   */
#define esp_cfg1    io_addr + 8  /* rw  First configuration register   0x20   */
#define esp_cfact   io_addr + 9  /* wo  Clock conversion factor        0x24   */
#define esp_ctest   io_addr + 10 /* wo  Chip test register             0x28   */
#define esp_cfg2    io_addr + 11 /* rw  Second configuration register  0x2c   */

    /* The following is only found on the 53C9X series SCSI chips */
#define esp_cfg3    io_addr + 12 /* rw  Third configuration register   0x30  */
#define esp_cfg4    io_addr + 13 /* rw  Fourth configuration register  0x34  */

    /* The following is found on all chips except the NCR53C90 (ESP100) */
#define esp_tchi    io_addr + 14 /* rw  High bits of transfer count    0x38  */
#define esp_uid     esp_tchi     /* ro  Unique ID code                 0x38  */
#define esp_fgrnd   io_addr + 15 /* rw  Data base for fifo             0x3c  */
};

#endif /* !defined(__i386__) */

/* Various revisions of the ESP board. */
enum esp_rev {
  esp100     = 0x00,  /* NCR53C90 - very broken */
  esp100a    = 0x01,  /* NCR53C90A */
  esp236     = 0x02,
  fas236     = 0x03,
  fas100a    = 0x04,
  fast       = 0x05,
  fas366     = 0x06,
  fas216     = 0x07,
  fsc        = 0x08,  /* SYM53C94-2 */
  espunknown = 0x09
};

/* We get one of these for each ESP probed. */
struct NCR_ESP {
  struct NCR_ESP *next;                   /* Next ESP on probed or NULL */
  struct ESP_regs *eregs;	          /* All esp registers */
  int dma;                                /* Who I do transfers with. */
  void *dregs;		  		  /* And his registers. */
  struct Scsi_Host *ehost;                /* Backpointer to SCSI Host */

  void *edev;        		          /* Pointer to controller base/SBus */
  int esp_id;                             /* Unique per-ESP ID number */

  /* ESP Configuration Registers */
  unsigned char config1;                  /* Copy of the 1st config register */
  unsigned char config2;                  /* Copy of the 2nd config register */
  unsigned char config3[16];              /* Copy of the 3rd config register */

  /* The current command we are sending to the ESP chip.  This esp_command
   * ptr needs to be mapped in DVMA area so we can send commands and read
   * from the ESP fifo without burning precious CPU cycles.  Programmed I/O
   * sucks when we have the DVMA to do it for us.  The ESP is stupid and will
   * only send out 6, 10, and 12 byte SCSI commands, others we need to send
   * one byte at a time.  esp_slowcmd being set says that we are doing one
   * of the command types ESP doesn't understand, esp_scmdp keeps track of
   * which byte we are sending, esp_scmdleft says how many bytes to go.
   */
  volatile unchar *esp_command;           /* Location of command (CPU view)  */
  __u32            esp_command_dvma;      /* Location of command (DVMA view) */
  unsigned char esp_clen;                 /* Length of this command */
  unsigned char esp_slowcmd;
  unsigned char *esp_scmdp;
  unsigned char esp_scmdleft;

  /* The following are used to determine the cause of an IRQ. Upon every
   * IRQ entry we synchronize these with the hardware registers.
   */
  unchar ireg;                            /* Copy of ESP interrupt register */
  unchar sreg;                            /* Same for ESP status register */
  unchar seqreg;                          /* The ESP sequence register */

  /* The following is set when a premature interrupt condition is detected