cs461x.h

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#ifndef __CS461X_H
#define __CS461X_H

/*
 *  Copyright (c) by Jaroslav Kysela <[e-mail]>
 *  Definitions for Cirrus Logic CS461x chips
 *
 *
 *   This program is free software; you can redistribute it and/or modify
 *   it under the terms of the GNU General Public License as published by
 *   the Free Software Foundation; either version 2 of the License, or
 *   (at your option) any later version.
 *
 *   This program is distributed in the hope that it will be useful,
 *   but WITHOUT ANY WARRANTY; without even the implied warranty of
 *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *   GNU General Public License for more details.
 *
 *   You should have received a copy of the GNU General Public License
 *   along with this program; if not, write to the Free Software
 *   Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 *
 */

#ifndef PCI_VENDOR_ID_CIRRUS
#define PCI_VENDOR_ID_CIRRUS            0x1013
#endif
#ifndef PCI_DEVICE_ID_CIRRUS_4610
#define PCI_DEVICE_ID_CIRRUS_4610       0x6001
#endif
#ifndef PCI_DEVICE_ID_CIRRUS_4612
#define PCI_DEVICE_ID_CIRRUS_4612       0x6003
#endif
#ifndef PCI_DEVICE_ID_CIRRUS_4615
#define PCI_DEVICE_ID_CIRRUS_4615       0x6004
#endif

/*
 *  Direct registers
 */

/*
 *  The following define the offsets of the registers accessed via base address
 *  register zero on the CS461x part.
 */
#define BA0_HISR				0x00000000
#define BA0_HSR0                                0x00000004
#define BA0_HICR                                0x00000008
#define BA0_DMSR                                0x00000100
#define BA0_HSAR                                0x00000110
#define BA0_HDAR                                0x00000114
#define BA0_HDMR                                0x00000118
#define BA0_HDCR                                0x0000011C
#define BA0_PFMC                                0x00000200
#define BA0_PFCV1                               0x00000204
#define BA0_PFCV2                               0x00000208
#define BA0_PCICFG00                            0x00000300
#define BA0_PCICFG04                            0x00000304
#define BA0_PCICFG08                            0x00000308
#define BA0_PCICFG0C                            0x0000030C
#define BA0_PCICFG10                            0x00000310
#define BA0_PCICFG14                            0x00000314
#define BA0_PCICFG18                            0x00000318
#define BA0_PCICFG1C                            0x0000031C
#define BA0_PCICFG20                            0x00000320
#define BA0_PCICFG24                            0x00000324
#define BA0_PCICFG28                            0x00000328
#define BA0_PCICFG2C                            0x0000032C
#define BA0_PCICFG30                            0x00000330
#define BA0_PCICFG34                            0x00000334
#define BA0_PCICFG38                            0x00000338
#define BA0_PCICFG3C                            0x0000033C
#define BA0_CLKCR1                              0x00000400
#define BA0_CLKCR2                              0x00000404
#define BA0_PLLM                                0x00000408
#define BA0_PLLCC                               0x0000040C
#define BA0_FRR                                 0x00000410 
#define BA0_CFL1                                0x00000414
#define BA0_CFL2                                0x00000418
#define BA0_SERMC1                              0x00000420
#define BA0_SERMC2                              0x00000424
#define BA0_SERC1                               0x00000428
#define BA0_SERC2                               0x0000042C
#define BA0_SERC3                               0x00000430
#define BA0_SERC4                               0x00000434
#define BA0_SERC5                               0x00000438
#define BA0_SERBSP                              0x0000043C
#define BA0_SERBST                              0x00000440
#define BA0_SERBCM                              0x00000444
#define BA0_SERBAD                              0x00000448
#define BA0_SERBCF                              0x0000044C
#define BA0_SERBWP                              0x00000450
#define BA0_SERBRP                              0x00000454
#ifndef NO_CS4612
#define BA0_ASER_FADDR                          0x00000458
#endif
#define BA0_ACCTL                               0x00000460
#define BA0_ACSTS                               0x00000464
#define BA0_ACOSV                               0x00000468
#define BA0_ACCAD                               0x0000046C
#define BA0_ACCDA                               0x00000470
#define BA0_ACISV                               0x00000474
#define BA0_ACSAD                               0x00000478
#define BA0_ACSDA                               0x0000047C
#define BA0_JSPT                                0x00000480
#define BA0_JSCTL                               0x00000484
#define BA0_JSC1                                0x00000488
#define BA0_JSC2                                0x0000048C
#define BA0_MIDCR                               0x00000490
#define BA0_MIDSR                               0x00000494
#define BA0_MIDWP                               0x00000498
#define BA0_MIDRP                               0x0000049C
#define BA0_JSIO                                0x000004A0
#ifndef NO_CS4612
#define BA0_ASER_MASTER                         0x000004A4
#endif
#define BA0_CFGI                                0x000004B0
#define BA0_SSVID                               0x000004B4
#define BA0_GPIOR                               0x000004B8
#ifndef NO_CS4612
#define BA0_EGPIODR                             0x000004BC
#define BA0_EGPIOPTR                            0x000004C0
#define BA0_EGPIOTR                             0x000004C4
#define BA0_EGPIOWR                             0x000004C8
#define BA0_EGPIOSR                             0x000004CC
#define BA0_SERC6                               0x000004D0
#define BA0_SERC7                               0x000004D4
#define BA0_SERACC                              0x000004D8
#define BA0_ACCTL2                              0x000004E0
#define BA0_ACSTS2                              0x000004E4
#define BA0_ACOSV2                              0x000004E8
#define BA0_ACCAD2                              0x000004EC
#define BA0_ACCDA2                              0x000004F0
#define BA0_ACISV2                              0x000004F4
#define BA0_ACSAD2                              0x000004F8
#define BA0_ACSDA2                              0x000004FC
#define BA0_IOTAC0                              0x00000500
#define BA0_IOTAC1                              0x00000504
#define BA0_IOTAC2                              0x00000508
#define BA0_IOTAC3                              0x0000050C
#define BA0_IOTAC4                              0x00000510
#define BA0_IOTAC5                              0x00000514
#define BA0_IOTAC6                              0x00000518
#define BA0_IOTAC7                              0x0000051C
#define BA0_IOTAC8                              0x00000520
#define BA0_IOTAC9                              0x00000524
#define BA0_IOTAC10                             0x00000528
#define BA0_IOTAC11                             0x0000052C
#define BA0_IOTFR0                              0x00000540
#define BA0_IOTFR1                              0x00000544
#define BA0_IOTFR2                              0x00000548
#define BA0_IOTFR3                              0x0000054C
#define BA0_IOTFR4                              0x00000550
#define BA0_IOTFR5                              0x00000554
#define BA0_IOTFR6                              0x00000558
#define BA0_IOTFR7                              0x0000055C
#define BA0_IOTFIFO                             0x00000580
#define BA0_IOTRRD                              0x00000584
#define BA0_IOTFP                               0x00000588
#define BA0_IOTCR                               0x0000058C
#define BA0_DPCID                               0x00000590
#define BA0_DPCIA                               0x00000594
#define BA0_DPCIC                               0x00000598
#define BA0_PCPCIR                              0x00000600
#define BA0_PCPCIG                              0x00000604
#define BA0_PCPCIEN                             0x00000608
#define BA0_EPCIPMC                             0x00000610
#endif

/*
 *  The following define the offsets of the registers and memories accessed via
 *  base address register one on the CS461x part.
 */
#define BA1_SP_DMEM0                            0x00000000
#define BA1_SP_DMEM1                            0x00010000
#define BA1_SP_PMEM                             0x00020000
#define BA1_SP_REG				0x00030000
#define BA1_SPCR                                0x00030000
#define BA1_DREG                                0x00030004
#define BA1_DSRWP                               0x00030008
#define BA1_TWPR                                0x0003000C
#define BA1_SPWR                                0x00030010
#define BA1_SPIR                                0x00030014
#define BA1_FGR1                                0x00030020
#define BA1_SPCS                                0x00030028
#define BA1_SDSR                                0x0003002C
#define BA1_FRMT                                0x00030030
#define BA1_FRCC                                0x00030034
#define BA1_FRSC                                0x00030038
#define BA1_OMNI_MEM                            0x000E0000

/*
 *  The following defines are for the flags in the host interrupt status
 *  register.
 */
#define HISR_VC_MASK                            0x0000FFFF
#define HISR_VC0                                0x00000001
#define HISR_VC1                                0x00000002
#define HISR_VC2                                0x00000004
#define HISR_VC3                                0x00000008
#define HISR_VC4                                0x00000010
#define HISR_VC5                                0x00000020
#define HISR_VC6                                0x00000040
#define HISR_VC7                                0x00000080
#define HISR_VC8                                0x00000100
#define HISR_VC9                                0x00000200
#define HISR_VC10                               0x00000400
#define HISR_VC11                               0x00000800
#define HISR_VC12                               0x00001000
#define HISR_VC13                               0x00002000
#define HISR_VC14                               0x00004000
#define HISR_VC15                               0x00008000
#define HISR_INT0                               0x00010000
#define HISR_INT1                               0x00020000
#define HISR_DMAI                               0x00040000
#define HISR_FROVR                              0x00080000
#define HISR_MIDI                               0x00100000
#ifdef NO_CS4612
#define HISR_RESERVED                           0x0FE00000
#else
#define HISR_SBINT                              0x00200000
#define HISR_RESERVED                           0x0FC00000
#endif
#define HISR_H0P                                0x40000000
#define HISR_INTENA                             0x80000000

/*
 *  The following defines are for the flags in the host signal register 0.
 */
#define HSR0_VC_MASK                            0xFFFFFFFF
#define HSR0_VC16                               0x00000001
#define HSR0_VC17                               0x00000002
#define HSR0_VC18                               0x00000004
#define HSR0_VC19                               0x00000008
#define HSR0_VC20                               0x00000010
#define HSR0_VC21                               0x00000020
#define HSR0_VC22                               0x00000040
#define HSR0_VC23                               0x00000080
#define HSR0_VC24                               0x00000100
#define HSR0_VC25                               0x00000200
#define HSR0_VC26                               0x00000400
#define HSR0_VC27                               0x00000800
#define HSR0_VC28                               0x00001000
#define HSR0_VC29                               0x00002000
#define HSR0_VC30                               0x00004000
#define HSR0_VC31                               0x00008000
#define HSR0_VC32                               0x00010000
#define HSR0_VC33                               0x00020000
#define HSR0_VC34                               0x00040000
#define HSR0_VC35                               0x00080000
#define HSR0_VC36                               0x00100000
#define HSR0_VC37                               0x00200000
#define HSR0_VC38                               0x00400000
#define HSR0_VC39                               0x00800000
#define HSR0_VC40                               0x01000000
#define HSR0_VC41                               0x02000000
#define HSR0_VC42                               0x04000000
#define HSR0_VC43                               0x08000000
#define HSR0_VC44                               0x10000000
#define HSR0_VC45                               0x20000000
#define HSR0_VC46                               0x40000000
#define HSR0_VC47                               0x80000000

/*
 *  The following defines are for the flags in the host interrupt control
 *  register.
 */
#define HICR_IEV                                0x00000001
#define HICR_CHGM                               0x00000002

/*
 *  The following defines are for the flags in the DMA status register.
 */
#define DMSR_HP                                 0x00000001
#define DMSR_HR                                 0x00000002
#define DMSR_SP                                 0x00000004
#define DMSR_SR                                 0x00000008

/*
 *  The following defines are for the flags in the host DMA source address
 *  register.
 */
#define HSAR_HOST_ADDR_MASK                     0xFFFFFFFF
#define HSAR_DSP_ADDR_MASK                      0x0000FFFF
#define HSAR_MEMID_MASK                         0x000F0000
#define HSAR_MEMID_SP_DMEM0                     0x00000000
#define HSAR_MEMID_SP_DMEM1                     0x00010000
#define HSAR_MEMID_SP_PMEM                      0x00020000
#define HSAR_MEMID_SP_DEBUG                     0x00030000
#define HSAR_MEMID_OMNI_MEM                     0x000E0000
#define HSAR_END                                0x40000000
#define HSAR_ERR                                0x80000000

/*
 *  The following defines are for the flags in the host DMA destination address
 *  register.
 */
#define HDAR_HOST_ADDR_MASK                     0xFFFFFFFF
#define HDAR_DSP_ADDR_MASK                      0x0000FFFF
#define HDAR_MEMID_MASK                         0x000F0000
#define HDAR_MEMID_SP_DMEM0                     0x00000000
#define HDAR_MEMID_SP_DMEM1                     0x00010000
#define HDAR_MEMID_SP_PMEM                      0x00020000
#define HDAR_MEMID_SP_DEBUG                     0x00030000
#define HDAR_MEMID_OMNI_MEM                     0x000E0000