amd7930.c

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/* $Id: amd7930.c,v 1.24 2000/01/22 05:10:27 anton Exp $
 * drivers/sbus/audio/amd7930.c
 *
 * Copyright (C) 1996,1997 Thomas K. Dyas ([e-mail])
 *
 * This is the lowlevel driver for the AMD7930 audio chip found on all
 * sun4c machines and some sun4m machines.
 *
 * The amd7930 is actually an ISDN chip which has a very simple
 * integrated audio encoder/decoder. When Sun decided on what chip to
 * use for audio, they had the brilliant idea of using the amd7930 and
 * only connecting the audio encoder/decoder pins.
 *
 * Thanks to the AMD engineer who was able to get us the AMD79C30
 * databook which has all the programming information and gain tables.
 *
 * Advanced Micro Devices' Am79C30A is an ISDN/audio chip used in the
 * SparcStation 1+.  The chip provides microphone and speaker interfaces
 * which provide mono-channel audio at 8K samples per second via either
 * 8-bit A-law or 8-bit mu-law encoding.  Also, the chip features an
 * ISDN BRI Line Interface Unit (LIU), I.430 S/T physical interface,
 * which performs basic D channel LAPD processing and provides raw
 * B channel data.  The digital audio channel, the two ISDN B channels,
 * and two 64 Kbps channels to the microprocessor are all interconnected
 * via a multiplexer.
 *
 * This driver interfaces to the Linux HiSax ISDN driver, which performs
 * all high-level Q.921 and Q.931 ISDN functions.  The file is not
 * itself a hardware driver; rather it uses functions exported by
 * the AMD7930 driver in the sparcaudio subsystem (drivers/sbus/audio),
 * allowing the chip to be simultaneously used for both audio and ISDN data.
 * The hardware driver does _no_ buffering, but provides several callbacks
 * which are called during interrupt service and should therefore run quickly.
 *
 * D channel transmission is performed by passing the hardware driver the
 * address and size of an skb's data area, then waiting for a callback
 * to signal successful transmission of the packet.  A task is then
 * queued to notify the HiSax driver that another packet may be transmitted.
 *
 * D channel reception is quite simple, mainly because of:
 *   1) the slow speed of the D channel - 16 kbps, and
 *   2) the presence of an 8- or 32-byte (depending on chip version) FIFO
 *      to buffer the D channel data on the chip
 * Worst case scenario of back-to-back packets with the 8 byte buffer
 * at 16 kbps yields an service time of 4 ms - long enough to preclude
 * the need for fancy buffering.  We queue a background task that copies
 * data out of the receive buffer into an skb, and the hardware driver
 * simply does nothing until we're done with the receive buffer and
 * reset it for a new packet.
 *
 * B channel processing is more complex, because of:
 *   1) the faster speed - 64 kbps,
 *   2) the lack of any on-chip buffering (it interrupts for every byte), and
 *   3) the lack of any chip support for HDLC encapsulation
 *
 * The HiSax driver can put each B channel into one of three modes -
 * L1_MODE_NULL (channel disabled), L1_MODE_TRANS (transparent data relay),
 * and L1_MODE_HDLC (HDLC encapsulation by low-level driver).
 * L1_MODE_HDLC is the most common, used for almost all "pure" digital
 * data sessions.  L1_MODE_TRANS is used for ISDN audio.
 *
 * HDLC B channel transmission is performed via a large buffer into
 * which the skb is copied while performing HDLC bit-stuffing.  A CRC
 * is computed and attached to the end of the buffer, which is then
 * passed to the low-level routines for raw transmission.  Once
 * transmission is complete, the hardware driver is set to enter HDLC
 * idle by successive transmission of mark (all 1) bytes, waiting for
 * the ISDN driver to prepare another packet for transmission and
 * deliver it.
 *
 * HDLC B channel reception is performed via an X-byte ring buffer
 * divided into N sections of X/N bytes each.  Defaults: X=256 bytes, N=4.
 * As the hardware driver notifies us that each section is full, we
 * hand it the next section and schedule a background task to peruse
 * the received section, bit-by-bit, with an HDLC decoder.  As
 * packets are detected, they are copied into a large buffer while
 * decoding HDLC bit-stuffing.  The ending CRC is verified, and if
 * it is correct, we alloc a new skb of the correct length (which we
 * now know), copy the packet into it, and hand it to the upper layers.
 * Optimization: for large packets, we hand the buffer (which also
 * happens to be an skb) directly to the upper layer after an skb_trim,
 * and alloc a new large buffer for future packets, thus avoiding a copy.
 * Then we return to HDLC processing; state is saved between calls.
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/errno.h>
#include <linux/interrupt.h>
#include <linux/malloc.h>
#include <linux/init.h>
#include <linux/version.h>
#include <linux/soundcard.h>
#include <asm/openprom.h>
#include <asm/oplib.h>
#include <asm/system.h>
#include <asm/irq.h>
#include <asm/io.h>
#include <asm/sbus.h>

#include <asm/audioio.h>
#include "amd7930.h"

static __u8  bilinear2mulaw(__u8 data);
static __u8  mulaw2bilinear(__u8 data);
static __u8  linear2mulaw(__u16 data);
static __u16 mulaw2linear(__u8 data);

#if defined (AMD79C30_ISDN) || defined (LINUX_VERSION_CODE) && LINUX_VERSION_CODE > 0x200ff 
#include "../../isdn/hisax/hisax.h"
#include "../../isdn/hisax/isdnl1.h"
#include "../../isdn/hisax/foreign.h"
#endif

#define MAX_DRIVERS 1

static struct sparcaudio_driver drivers[MAX_DRIVERS];
static int num_drivers;

/* Each amd7930 chip has two bi-directional B channels and a D
 * channel available to the uproc.  This structure handles all
 * the buffering needed to transmit and receive via a single channel.
 */

#define CHANNEL_AVAILABLE	0x00
#define CHANNEL_INUSE_AUDIO_IN	0x01
#define CHANNEL_INUSE_AUDIO_OUT	0x02
#define CHANNEL_INUSE_ISDN_B1	0x04
#define CHANNEL_INUSE_ISDN_B2	0x08
#define CHANNEL_INUSE		0xff

struct amd7930_channel {
	/* Channel status */
	u8 channel_status;

	/* Current buffer that the driver is playing on channel */
	volatile __u8 * output_ptr;
	volatile u32 output_count;
	u8 xmit_idle_char;

	/* Callback routine (and argument) when output is done on */
	void (*output_callback)(void *, unsigned char);
	void * output_callback_arg;

	/* Current buffer that the driver is recording on channel */
	volatile __u8 * input_ptr;
	volatile u32 input_count;
	volatile u32 input_limit;

	/* Callback routine (and argument) when input is done on */
	void (*input_callback)(void *, unsigned char, unsigned long);
	void * input_callback_arg;

	int input_format;
	int output_format;
};

/* Private information we store for each amd7930 chip. */
struct amd7930_info {
	struct amd7930_channel D;
	struct amd7930_channel Bb;
	struct amd7930_channel Bc;

	/* Pointers to which B channels are being used for what
	 * These three fields (Baudio, Bisdn[0], and Bisdn[1]) will either
	 * be NULL or point to one of the Bb/Bc structures above.
	 */
	struct amd7930_channel *Baudio;
	struct amd7930_channel *Bisdn[2];

	/* Device registers information. */
	unsigned long regs;
	unsigned long regs_size;
	struct amd7930_map map;

	/* Volume information. */
	int pgain, rgain, mgain;

	/* Device interrupt information. */
	int irq;
	volatile int ints_on;

	/* Format type */
	int format_type;

	/* Someone to signal when the ISDN LIU state changes */
	int liu_state;
	void (*liu_callback)(void *);
	void *liu_callback_arg;
};

/* Output a 16-bit quantity in the order that the amd7930 expects. */
static __inline__ void amd7930_out16(unsigned long regs, u16 val)
{
	sbus_writeb(val & 0xff, regs + DR);
	sbus_writeb(val >> 8, regs + DR);
}

/* gx, gr & stg gains.  this table must contain 256 elements with
 * the 0th being "infinity" (the magic value 9008).  The remaining
 * elements match sun's gain curve (but with higher resolution):
 * -18 to 0dB in .16dB steps then 0 to 12dB in .08dB steps.
 */
static __const__ __u16 gx_coeff[256] = {
	0x9008, 0x8b7c, 0x8b51, 0x8b45, 0x8b42, 0x8b3b, 0x8b36, 0x8b33,
	0x8b32, 0x8b2a, 0x8b2b, 0x8b2c, 0x8b25, 0x8b23, 0x8b22, 0x8b22,
	0x9122, 0x8b1a, 0x8aa3, 0x8aa3, 0x8b1c, 0x8aa6, 0x912d, 0x912b,
	0x8aab, 0x8b12, 0x8aaa, 0x8ab2, 0x9132, 0x8ab4, 0x913c, 0x8abb,
	0x9142, 0x9144, 0x9151, 0x8ad5, 0x8aeb, 0x8a79, 0x8a5a, 0x8a4a,
	0x8b03, 0x91c2, 0x91bb, 0x8a3f, 0x8a33, 0x91b2, 0x9212, 0x9213,
	0x8a2c, 0x921d, 0x8a23, 0x921a, 0x9222, 0x9223, 0x922d, 0x9231,
	0x9234, 0x9242, 0x925b, 0x92dd, 0x92c1, 0x92b3, 0x92ab, 0x92a4,
	0x92a2, 0x932b, 0x9341, 0x93d3, 0x93b2, 0x93a2, 0x943c, 0x94b2,
	0x953a, 0x9653, 0x9782, 0x9e21, 0x9d23, 0x9cd2, 0x9c23, 0x9baa,
	0x9bde, 0x9b33, 0x9b22, 0x9b1d, 0x9ab2, 0xa142, 0xa1e5, 0x9a3b,
	0xa213, 0xa1a2, 0xa231, 0xa2eb, 0xa313, 0xa334, 0xa421, 0xa54b,
	0xada4, 0xac23, 0xab3b, 0xaaab, 0xaa5c, 0xb1a3, 0xb2ca, 0xb3bd,
	0xbe24, 0xbb2b, 0xba33, 0xc32b, 0xcb5a, 0xd2a2, 0xe31d, 0x0808,
	0x72ba, 0x62c2, 0x5c32, 0x52db, 0x513e, 0x4cce, 0x43b2, 0x4243,
	0x41b4, 0x3b12, 0x3bc3, 0x3df2, 0x34bd, 0x3334, 0x32c2, 0x3224,
	0x31aa, 0x2a7b, 0x2aaa, 0x2b23, 0x2bba, 0x2c42, 0x2e23, 0x25bb,
	0x242b, 0x240f, 0x231a, 0x22bb, 0x2241, 0x2223, 0x221f, 0x1a33,
	0x1a4a, 0x1acd, 0x2132, 0x1b1b, 0x1b2c, 0x1b62, 0x1c12, 0x1c32,
	0x1d1b, 0x1e71, 0x16b1, 0x1522, 0x1434, 0x1412, 0x1352, 0x1323,
	0x1315, 0x12bc, 0x127a, 0x1235, 0x1226, 0x11a2, 0x1216, 0x0a2a,
	0x11bc, 0x11d1, 0x1163, 0x0ac2, 0x0ab2, 0x0aab, 0x0b1b, 0x0b23,
	0x0b33, 0x0c0f, 0x0bb3, 0x0c1b, 0x0c3e, 0x0cb1, 0x0d4c, 0x0ec1,
	0x079a, 0x0614, 0x0521, 0x047c, 0x0422, 0x03b1, 0x03e3, 0x0333,
	0x0322, 0x031c, 0x02aa, 0x02ba, 0x02f2, 0x0242, 0x0232, 0x0227,
	0x0222, 0x021b, 0x01ad, 0x0212, 0x01b2, 0x01bb, 0x01cb, 0x01f6,
	0x0152, 0x013a, 0x0133, 0x0131, 0x012c, 0x0123, 0x0122, 0x00a2,
	0x011b, 0x011e, 0x0114, 0x00b1, 0x00aa, 0x00b3, 0x00bd, 0x00ba,
	0x00c5, 0x00d3, 0x00f3, 0x0062, 0x0051, 0x0042, 0x003b, 0x0033,
	0x0032, 0x002a, 0x002c, 0x0025, 0x0023, 0x0022, 0x001a, 0x0021,
	0x001b, 0x001b, 0x001d, 0x0015, 0x0013, 0x0013, 0x0012, 0x0012,
	0x000a, 0x000a, 0x0011, 0x0011, 0x000b, 0x000b, 0x000c, 0x000e,
};

static __const__ __u16 ger_coeff[] = {
	0x431f, /* 5. dB */
	0x331f, /* 5.5 dB */
	0x40dd, /* 6. dB */
	0x11dd, /* 6.5 dB */
	0x440f, /* 7. dB */
	0x411f, /* 7.5 dB */
	0x311f, /* 8. dB */
	0x5520, /* 8.5 dB */
	0x10dd, /* 9. dB */
	0x4211, /* 9.5 dB */
	0x410f, /* 10. dB */
	0x111f, /* 10.5 dB */
	0x600b, /* 11. dB */
	0x00dd, /* 11.5 dB */
	0x4210, /* 12. dB */
	0x110f, /* 13. dB */
	0x7200, /* 14. dB */
	0x2110, /* 15. dB */
	0x2200, /* 15.9 dB */
	0x000b, /* 16.9 dB */
	0x000f  /* 18. dB */
};
#define NR_GER_COEFFS (sizeof(ger_coeff) / sizeof(ger_coeff[0]))

/* Enable amd7930 interrupts atomically. */
static void amd7930_enable_ints(struct amd7930_info *info)
{
	unsigned long flags;

	save_and_cli(flags);
	if (!info->ints_on) {
		sbus_writeb(AMR_INIT, info->regs + CR);
		sbus_writeb(AM_INIT_ACTIVE, info->regs + DR);
		info->ints_on = 1;
	}
	restore_flags(flags);
}

/* Disable amd7930 interrupts atomically. */
static __inline__ void amd7930_disable_ints(struct amd7930_info *info)
{
	unsigned long flags;

	save_and_cli(flags);
	if (info->ints_on) {
		sbus_writeb(AMR_INIT, info->regs + CR);
		sbus_writeb(AM_INIT_ACTIVE | AM_INIT_DISABLE_INTS,
			    info->regs + DR);
		info->ints_on = 0;
	}
	restore_flags(flags);

}  

/* Idle amd7930 (no interrupts, no audio, no data) */
static __inline__ void amd7930_idle(struct amd7930_info *info)
{
	unsigned long flags;

	save_and_cli(flags);
	if (info->ints_on) {
		sbus_writeb(AMR_INIT, info->regs + CR);
		sbus_writeb(0, info->regs + DR);
		info->ints_on = 0;
	}
	restore_flags(flags);
}  

/* Commit the local copy of the MAP registers to the amd7930. */
static void amd7930_write_map(struct sparcaudio_driver *drv)
{
	struct amd7930_info *info = (struct amd7930_info *) drv->private;
	unsigned long        regs = info->regs;
	struct amd7930_map  *map  = &info->map;
	unsigned long flags;

	save_and_cli(flags);

	sbus_writeb(AMR_MAP_GX, regs + CR);
	amd7930_out16(regs, map->gx);

	sbus_writeb(AMR_MAP_GR, regs + CR);
	amd7930_out16(regs, map->gr);

	sbus_writeb(AMR_MAP_STGR, regs + CR);
	amd7930_out16(regs, map->stgr);

	sbus_writeb(AMR_MAP_GER, regs + CR);
	amd7930_out16(regs, map->ger);

	sbus_writeb(AMR_MAP_MMR1, regs + CR);
	sbus_writeb(map->mmr1, regs + DR);

	sbus_writeb(AMR_MAP_MMR2, regs + CR);
	sbus_writeb(map->mmr2, regs + DR);

	restore_flags(flags);
}

/* Update the MAP registers with new settings. */
static void amd7930_update_map(struct sparcaudio_driver *drv)
{
	struct amd7930_info *info = (struct amd7930_info *) drv->private;
	struct amd7930_map  *map  = &info->map;
	int level;

	map->gx = gx_coeff[info->rgain];
	map->stgr = gx_coeff[info->mgain];

	level = (info->pgain * (256 + NR_GER_COEFFS)) >> 8;
	if (level >= 256) {
		map->ger = ger_coeff[level - 256];
		map->gr = gx_coeff[255];
	} else {
		map->ger = ger_coeff[0];
		map->gr = gx_coeff[level];
	}

	amd7930_write_map(drv);
}

/* Bit of a hack here - if the HISAX ISDN driver has got INTSTAT debugging
 * turned on, we send debugging characters to the ISDN driver:
 *
 *   i# - Interrupt received - number from 0 to 7 is low three bits of IR
 *   >  - Loaded a single char into the Dchan xmit FIFO
 *   +  - Finished loading an xmit packet into the Dchan xmit FIFO
 *   <  - Read a single char from the Dchan recv FIFO
 *   !  - Finished reading a packet from the Dchan recv FIFO
 *
 * This code needs to be removed if anything other than HISAX uses the ISDN
 * driver, since D.output_callback_arg is assumed to be a certain struct ptr
 */

#ifdef L2FRAME_DEBUG

inline void debug_info(struct amd7930_info *info, char c)
{
	struct IsdnCardState *cs;

	if (!info || !info->D.output_callback_arg)
		return;

	cs = (struct IsdnCardState *) info->D.output_callback_arg;

	if (!cs || !cs->status_write)
		return;

	if (cs->debug & L1_DEB_INTSTAT) {
		*(cs->status_write++) = c;
		if (cs->status_write > cs->status_end)
			cs->status_write = cs->status_buf;
	}
}

#else

#define debug_info(info,c)

#endif

static void fill_D_xmit_fifo(struct amd7930_info *info)
{
	/* Send next byte(s) of outgoing data. */
	while (info->D.output_ptr && info->D.output_count > 0 &&
               (sbus_readb(info->regs + DSR2) & AMR_DSR2_TBE)) {
		u8 byte = *(info->D.output_ptr);

		/* Send the next byte and advance buffer pointer. */
		sbus_writeb(byte, info->regs + DCTB);
		info->D.output_ptr++;
		info->D.output_count--;

		debug_info(info, '>');
        }
}

static void transceive_Dchannel(struct amd7930_info *info)
{
	__u8 dummy;

#define D_XMIT_ERRORS (AMR_DER_COLLISION | AMR_DER_UNRN)
#define D_RECV_ERRORS (AMR_DER_RABRT | AMR_DER_RFRAME | AMR_DER_FCS | \
			AMR_DER_OVFL | AMR_DER_UNFL | AMR_DER_OVRN)

	/* Transmit if we can */
	fill_D_xmit_fifo(info);

	/* Done with the xmit buffer? Notify the midlevel driver. */
	if (info->D.output_ptr != NULL && info->D.output_count == 0) {
		info->D.output_ptr = NULL;
		info->D.output_count = 0;
		debug_info(info, '+');
		if (info->D.output_callback)
			(*info->D.output_callback)
				(info->D.output_callback_arg,
				 sbus_readb(info->regs + DER));
				 /* sbus_readb(info->regs + DER) & D_XMIT_ERRORS); */
	}

	/* Read the next byte(s) of incoming data. */

	while (sbus_readb(info->regs + DSR2) & AMR_DSR2_RBA) {
		if (info->D.input_ptr &&
		    (info->D.input_count < info->D.input_limit)) {
			/* Get the next byte and advance buffer pointer. */
			*(info->D.input_ptr) = sbus_readb(info->regs + DCRB);
			info->D.input_ptr++;
			info->D.input_count++;
		} else {
			/* Overflow - should be detected by chip via RBLR
			 * so we'll just consume data until we see LBRP
			 */
			dummy = sbus_readb(info->regs + DCRB);
		}

		debug_info(info, '<');

		if (sbus_readb(info->regs + DSR2) & AMR_DSR2_LBRP) {
			__u8 der;

			/* End of recv packet? Notify the midlevel driver. */
			debug_info(info, '!');
			info->D.input_ptr = NULL;
			der = sbus_readb(info->regs + DER) & D_RECV_ERRORS;

			/* Read receive byte count - advances FIFOs */
			sbus_writeb(AMR_DLC_DRCR, info->regs + CR);
			dummy = sbus_readb(info->regs + DR);
			dummy = sbus_readb(info->regs + DR);

			if (info->D.input_callback)
				(*info->D.input_callback)
					(info->D.input_callback_arg, der,
					 info->D.input_count);