math.c

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	return (would_trap ? 0 : 1);
}

typedef union {
	u32 s;
	u64 d;
	u64 q[2];
} *argp;

static int do_one_mathemu(u32 insn, unsigned long *pfsr, unsigned long *fregs)
{
	/* Emulate the given insn, updating fsr and fregs appropriately. */
	int type = 0;
	/* r is rd, b is rs2 and a is rs1. The *u arg tells
	   whether the argument should be packed/unpacked (0 - do not unpack/pack, 1 - unpack/pack)
	   non-u args tells the size of the argument (0 - no argument, 1 - single, 2 - double, 3 - quad */
#define TYPE(dummy, r, ru, b, bu, a, au) type = (au << 2) | (a << 0) | (bu << 5) | (b << 3) | (ru << 8) | (r << 6)
	int freg;
	argp rs1 = NULL, rs2 = NULL, rd = NULL;
	FP_DECL_EX;
	FP_DECL_S(SA); FP_DECL_S(SB); FP_DECL_S(SR);
	FP_DECL_D(DA); FP_DECL_D(DB); FP_DECL_D(DR);
	FP_DECL_Q(QA); FP_DECL_Q(QB); FP_DECL_Q(QR);
	int IR;
	long fsr;

#ifdef DEBUG_MATHEMU
	printk("In do_mathemu(), emulating %08lx\n", insn);
#endif

	if ((insn & 0xc1f80000) == 0x81a00000)	/* FPOP1 */ {
		switch ((insn >> 5) & 0x1ff) {
		case FSQRTQ: TYPE(3,3,1,3,1,0,0); break;
		case FADDQ:
		case FSUBQ:
		case FMULQ:
		case FDIVQ: TYPE(3,3,1,3,1,3,1); break;
		case FDMULQ: TYPE(3,3,1,2,1,2,1); break;
		case FQTOS: TYPE(3,1,1,3,1,0,0); break;
		case FQTOD: TYPE(3,2,1,3,1,0,0); break;
		case FITOQ: TYPE(3,3,1,1,0,0,0); break;
		case FSTOQ: TYPE(3,3,1,1,1,0,0); break;
		case FDTOQ: TYPE(3,3,1,2,1,0,0); break;
		case FQTOI: TYPE(3,1,0,3,1,0,0); break;
		case FSQRTS: TYPE(2,1,1,1,1,0,0); break;
		case FSQRTD: TYPE(2,2,1,2,1,0,0); break;
		case FADDD:
		case FSUBD:
		case FMULD:
		case FDIVD: TYPE(2,2,1,2,1,2,1); break;
		case FADDS:
		case FSUBS:
		case FMULS:
		case FDIVS: TYPE(2,1,1,1,1,1,1); break;
		case FSMULD: TYPE(2,2,1,1,1,1,1); break;
		case FDTOS: TYPE(2,1,1,2,1,0,0); break;
		case FSTOD: TYPE(2,2,1,1,1,0,0); break;
		case FSTOI: TYPE(2,1,0,1,1,0,0); break;
		case FDTOI: TYPE(2,1,0,2,1,0,0); break;
		case FITOS: TYPE(2,1,1,1,0,0,0); break;
		case FITOD: TYPE(2,2,1,1,0,0,0); break;
		case FMOVS:
		case FABSS:
		case FNEGS: TYPE(2,1,0,1,0,0,0); break;
		default:
#ifdef DEBUG_MATHEMU
			printk("unknown FPop1: %03lx\n",(insn>>5)&0x1ff);
#endif
		}
	} else if ((insn & 0xc1f80000) == 0x81a80000)	/* FPOP2 */ {
		switch ((insn >> 5) & 0x1ff) {
		case FCMPS: TYPE(3,0,0,1,1,1,1); break;
		case FCMPES: TYPE(3,0,0,1,1,1,1); break;
		case FCMPD: TYPE(3,0,0,2,1,2,1); break;
		case FCMPED: TYPE(3,0,0,2,1,2,1); break;
		case FCMPQ: TYPE(3,0,0,3,1,3,1); break;
		case FCMPEQ: TYPE(3,0,0,3,1,3,1); break;
		default:
#ifdef DEBUG_MATHEMU
			printk("unknown FPop2: %03lx\n",(insn>>5)&0x1ff);
#endif
		}
	}

	if (!type) {	/* oops, didn't recognise that FPop */
#ifdef DEBUG_MATHEMU
		printk("attempt to emulate unrecognised FPop!\n");
#endif
		return 0;
	}

	/* Decode the registers to be used */
	freg = (*pfsr >> 14) & 0xf;

	*pfsr &= ~0x1c000;				/* clear the traptype bits */
	
	freg = ((insn >> 14) & 0x1f);
	switch (type & 0x3) {				/* is rs1 single, double or quad? */
	case 3:
		if (freg & 3) {				/* quadwords must have bits 4&5 of the */
							/* encoded reg. number set to zero. */
			*pfsr |= (6 << 14);
			return 0;			/* simulate invalid_fp_register exception */
		}
	/* fall through */
	case 2:
		if (freg & 1) {				/* doublewords must have bit 5 zeroed */
			*pfsr |= (6 << 14);
			return 0;
		}
	}
	rs1 = (argp)&fregs[freg];
	switch (type & 0x7) {
	case 7: FP_UNPACK_QP (QA, rs1); break;
	case 6: FP_UNPACK_DP (DA, rs1); break;
	case 5: FP_UNPACK_SP (SA, rs1); break;
	}
	freg = (insn & 0x1f);
	switch ((type >> 3) & 0x3) {			/* same again for rs2 */
	case 3:
		if (freg & 3) {				/* quadwords must have bits 4&5 of the */
							/* encoded reg. number set to zero. */
			*pfsr |= (6 << 14);
			return 0;			/* simulate invalid_fp_register exception */
		}
	/* fall through */
	case 2:
		if (freg & 1) {				/* doublewords must have bit 5 zeroed */
			*pfsr |= (6 << 14);
			return 0;
		}
	}
	rs2 = (argp)&fregs[freg];
	switch ((type >> 3) & 0x7) {
	case 7: FP_UNPACK_QP (QB, rs2); break;
	case 6: FP_UNPACK_DP (DB, rs2); break;
	case 5: FP_UNPACK_SP (SB, rs2); break;
	}
	freg = ((insn >> 25) & 0x1f);
	switch ((type >> 6) & 0x3) {			/* and finally rd. This one's a bit different */
	case 0:						/* dest is fcc. (this must be FCMPQ or FCMPEQ) */
		if (freg) {				/* V8 has only one set of condition codes, so */
							/* anything but 0 in the rd field is an error */
			*pfsr |= (6 << 14);		/* (should probably flag as invalid opcode */
			return 0;			/* but SIGFPE will do :-> ) */
		}
		break;
	case 3:
		if (freg & 3) {				/* quadwords must have bits 4&5 of the */
							/* encoded reg. number set to zero. */
			*pfsr |= (6 << 14);
			return 0;			/* simulate invalid_fp_register exception */
		}
	/* fall through */
	case 2:
		if (freg & 1) {				/* doublewords must have bit 5 zeroed */
			*pfsr |= (6 << 14);
			return 0;
		}
	/* fall through */
	case 1:
		rd = (void *)&fregs[freg];
		break;
	}
#ifdef DEBUG_MATHEMU
	printk("executing insn...\n");
#endif
	/* do the Right Thing */
	switch ((insn >> 5) & 0x1ff) {
	/* + */
	case FADDS: FP_ADD_S (SR, SA, SB); break;
	case FADDD: FP_ADD_D (DR, DA, DB); break;
	case FADDQ: FP_ADD_Q (QR, QA, QB); break;
	/* - */
	case FSUBS: FP_SUB_S (SR, SA, SB); break;
	case FSUBD: FP_SUB_D (DR, DA, DB); break;
	case FSUBQ: FP_SUB_Q (QR, QA, QB); break;
	/* * */
	case FMULS: FP_MUL_S (SR, SA, SB); break;
	case FSMULD: FP_CONV (D, S, 2, 1, DA, SA);
		     FP_CONV (D, S, 2, 1, DB, SB);
	case FMULD: FP_MUL_D (DR, DA, DB); break;
	case FDMULQ: FP_CONV (Q, D, 4, 2, QA, DA);
		     FP_CONV (Q, D, 4, 2, QB, DB);
	case FMULQ: FP_MUL_Q (QR, QA, QB); break;
	/* / */
	case FDIVS: FP_DIV_S (SR, SA, SB); break;
	case FDIVD: FP_DIV_D (DR, DA, DB); break;
	case FDIVQ: FP_DIV_Q (QR, QA, QB); break;
	/* sqrt */
	case FSQRTS: FP_SQRT_S (SR, SB); break;
	case FSQRTD: FP_SQRT_D (DR, DB); break;
	case FSQRTQ: FP_SQRT_Q (QR, QB); break;
	/* mov */
	case FMOVS: rd->s = rs2->s; break;
	case FABSS: rd->s = rs2->s & 0x7fffffff; break;
	case FNEGS: rd->s = rs2->s ^ 0x80000000; break;
	/* float to int */
	case FSTOI: FP_TO_INT_S (IR, SB, 32, 1); break;
	case FDTOI: FP_TO_INT_D (IR, DB, 32, 1); break;
	case FQTOI: FP_TO_INT_Q (IR, QB, 32, 1); break;
	/* int to float */
	case FITOS: IR = rs2->s; FP_FROM_INT_S (SR, IR, 32, int); break;
	case FITOD: IR = rs2->s; FP_FROM_INT_D (DR, IR, 32, int); break;
	case FITOQ: IR = rs2->s; FP_FROM_INT_Q (QR, IR, 32, int); break;
	/* float to float */
	case FSTOD: FP_CONV (D, S, 2, 1, DR, SB); break;
	case FSTOQ: FP_CONV (Q, S, 4, 1, QR, SB); break;
	case FDTOQ: FP_CONV (Q, D, 4, 2, QR, DB); break;
	case FDTOS: FP_CONV (S, D, 1, 2, SR, DB); break;
	case FQTOS: FP_CONV (S, Q, 1, 4, SR, QB); break;
	case FQTOD: FP_CONV (D, Q, 2, 4, DR, QB); break;
	/* comparison */
	case FCMPS:
	case FCMPES:
		FP_CMP_S(IR, SB, SA, 3);
		if (IR == 3 &&
		    (((insn >> 5) & 0x1ff) == FCMPES ||
		     FP_ISSIGNAN_S(SA) ||
		     FP_ISSIGNAN_S(SB)))
			FP_SET_EXCEPTION (FP_EX_INVALID);
		break;
	case FCMPD:
	case FCMPED:
		FP_CMP_D(IR, DB, DA, 3);
		if (IR == 3 &&
		    (((insn >> 5) & 0x1ff) == FCMPED ||
		     FP_ISSIGNAN_D(DA) ||
		     FP_ISSIGNAN_D(DB)))
			FP_SET_EXCEPTION (FP_EX_INVALID);
		break;
	case FCMPQ:
	case FCMPEQ:
		FP_CMP_Q(IR, QB, QA, 3);
		if (IR == 3 &&
		    (((insn >> 5) & 0x1ff) == FCMPEQ ||
		     FP_ISSIGNAN_Q(QA) ||
		     FP_ISSIGNAN_Q(QB)))
			FP_SET_EXCEPTION (FP_EX_INVALID);
	}
	if (!FP_INHIBIT_RESULTS) {
		switch ((type >> 6) & 0x7) {
		case 0: fsr = *pfsr;
			if (IR == -1) IR = 2;
			/* fcc is always fcc0 */
			fsr &= ~0xc00; fsr |= (IR << 10); break;
			*pfsr = fsr;
			break;
		case 1: rd->s = IR; break;
		case 5: FP_PACK_SP (rd, SR); break;
		case 6: FP_PACK_DP (rd, DR); break;
		case 7: FP_PACK_QP (rd, QR); break;
		}
	}
	if(_fex == 0)
		return 1;				/* success! */
	return record_exception(pfsr, _fex);
}