sba_iommu.c

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/*
**  System Bus Adapter (SBA) I/O MMU manager
**
**	(c) Copyright 2000 Grant Grundler
**	(c) Copyright 2000 Hewlett-Packard Company
**
**	Portions (c) 1999 Dave S. Miller (from sparc64 I/O MMU code)
**
**	This program is free software; you can redistribute it and/or modify
**	it under the terms of the GNU General Public License as published by
**      the Free Software Foundation; either version 2 of the License, or
**      (at your option) any later version.
**
**
** This module initializes the IOC (I/O Controller) found on B1000/C3000/
** J5000/J7000/N-class/L-class machines and their successors.
**
** FIXME: Multi-IOC support missing - depends on hp_device data
** FIXME: add DMA hint support programming in both sba and lba modules.
*/

#include <linux/config.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/spinlock.h>
#include <linux/malloc.h>
#include <linux/init.h>

#include <linux/mm.h>
#include <linux/string.h>
#define PCI_DEBUG		/* for ASSERT */
#include <linux/pci.h>
#undef PCI_DEBUG

#include <asm/byteorder.h>
#include <asm/io.h>
#include <asm/dma.h>		/* for DMA_CHUNK_SIZE */

#include <asm/hardware.h>	/* for register_driver() stuff */
#include <asm/gsc.h>		/* FIXME: for gsc_read/gsc_write */

#include <linux/proc_fs.h>
#include <asm/runway.h>		/* for proc_runway_root */


#define MODULE_NAME "SBA"

/*
** The number of debug flags is a clue - this code is fragile.
** Don't even think about messing with it unless you have
** plenty of 710's to sacrafice to the computer gods. :^)
*/
#undef DEBUG_SBA_INIT
#undef DEBUG_SBA_RUN
#undef DEBUG_SBA_RUN_SG
#undef DEBUG_SBA_RESOURCE
#undef ASSERT_PDIR_SANITY
#undef DEBUG_LARGE_SG_ENTRIES

#if 1
#define SBA_INLINE
#else
#define SBA_INLINE	__inline__
#endif

#ifdef DEBUG_SBA_INIT
#define DBG_INIT(x...)	printk(x)
#else
#define DBG_INIT(x...)
#endif

#ifdef DEBUG_SBA_RUN
#define DBG_RUN(x...)	printk(x)
#else
#define DBG_RUN(x...)
#endif

#ifdef DEBUG_SBA_RUN_SG
#define DBG_RUN_SG(x...)	printk(x)
#else
#define DBG_RUN_SG(x...)
#endif


#ifdef DEBUG_SBA_RESOURCE
#define DBG_RES(x...)	printk(x)
#else
#define DBG_RES(x...)
#endif

/*
** The number of pdir entries to "free" before issueing
** a read to PCOM register to flush out PCOM writes.
** Interacts with allocation granularity (ie 4 or 8 entries
** allocated and free'd/purged at a time might make this
** less interesting).
*/
#if 0
#define DELAYED_RESOURCE_CNT	16
#else
#undef DELAYED_RESOURCE_CNT
#endif

#define DEFAULT_DMA_HINT_REG	0

#define ASTRO_RUNWAY_PORT    0x582
#define ASTRO_ROPES_PORT     0x780

#define IKE_MERCED_PORT      0x803
#define IKE_ROPES_PORT       0x781

int sba_driver_callback(struct hp_device *, struct pa_iodc_driver *);

static struct pa_iodc_driver sba_drivers_for[] = {

/* FIXME: why is SVERSION checked? */

   {HPHW_IOA, ASTRO_RUNWAY_PORT, 0x0, 0xb, 0, 0x10,
		DRIVER_CHECK_HVERSION +
		DRIVER_CHECK_SVERSION + DRIVER_CHECK_HWTYPE,
                MODULE_NAME, "I/O MMU", (void *) sba_driver_callback},

   {HPHW_BCPORT, ASTRO_ROPES_PORT, 0x0, 0xb, 0, 0x10,
		DRIVER_CHECK_HVERSION +
		DRIVER_CHECK_SVERSION + DRIVER_CHECK_HWTYPE,
                MODULE_NAME, "I/O MMU", (void *) sba_driver_callback},

#if 0
/* FIXME : N-class! Use a different "callback"? */
   {HPHW_BCPORT, IKE_MERCED_PORT, 0x0, 0xb, 0, 0x10,
		DRIVER_CHECK_HVERSION +
		DRIVER_CHECK_SVERSION + DRIVER_CHECK_HWTYPE,
                MODULE_NAME, "I/O MMU", (void *) sba_driver_callback},

   {HPHW_BCPORT, IKE_ROPES_PORT, 0x0, 0xb, 0, 0x10,
		DRIVER_CHECK_HVERSION +
		DRIVER_CHECK_SVERSION + DRIVER_CHECK_HWTYPE,
                MODULE_NAME, "I/O MMU", (void *) sba_driver_callback},
#endif

   {0,0,0,0,0,0,
   0,
   (char *) NULL, (char *) NULL, (void *) NULL }
};


#define SBA_FUNC_ID	0x0000	/* function id */
#define SBA_FCLASS	0x0008	/* function class, bist, header, rev... */

#define IS_ASTRO(id) ( \
    (((id)->hw_type == HPHW_IOA) && ((id)->hversion == ASTRO_RUNWAY_PORT)) || \
    (((id)->hw_type == HPHW_BCPORT) && ((id)->hversion == ASTRO_ROPES_PORT))  \
)

#define CONFIG_FUNC_SIZE 4096   /* SBA configuration function reg set */

#define ASTRO_IOC_OFFSET 0x20000
/* Ike's IOC's occupy functions 2 and 3 (not 0 and 1) */
#define IKE_IOC_OFFSET(p) ((p+2)*CONFIG_FUNC_SIZE)

#define IOC_CTRL          0x8	/* IOC_CTRL offset */
#define IOC_CTRL_TE       (0x1 << 0) /* TOC Enable */
#define IOC_CTRL_RM       (0x1 << 8) /* Real Mode */
#define IOC_CTRL_NC       (0x1 << 9) /* Non Coherent Mode */

#define MAX_IOC		2	/* per Ike. Astro only has 1 */


/*
** Offsets into MBIB (Function 0 on Ike and hopefully Astro)
** Firmware programs this stuff. Don't touch it.
*/
#define IOS_DIST_BASE	0x390
#define IOS_DIST_MASK	0x398
#define IOS_DIST_ROUTE	0x3A0

#define IOS_DIRECT_BASE	0x3C0
#define IOS_DIRECT_MASK	0x3C8
#define IOS_DIRECT_ROUTE 0x3D0

/*
** Offsets into I/O TLB (Function 2 and 3 on Ike)
*/
#define ROPE0_CTL	0x200  /* "regbus pci0" */
#define ROPE1_CTL	0x208
#define ROPE2_CTL	0x210
#define ROPE3_CTL	0x218
#define ROPE4_CTL	0x220
#define ROPE5_CTL	0x228
#define ROPE6_CTL	0x230
#define ROPE7_CTL	0x238

#define HF_ENABLE	0x40


#define IOC_IBASE	0x300	/* IO TLB */
#define IOC_IMASK	0x308
#define IOC_PCOM	0x310
#define IOC_TCNFG	0x318
#define IOC_PDIR_BASE	0x320

#define IOC_IOVA_SPACE_BASE	0	/* IOVA ranges start at 0 */

/*
** IOC supports 4/8/16/64KB page sizes (see TCNFG register)
** It's safer (avoid memory corruption) to keep DMA page mappings
** equivalently sized to VM PAGE_SIZE.
**
** We really can't avoid generating a new mapping for each
** page since the Virtual Coherence Index has to be generated
** and updated for each page.
**
** IOVP_SIZE could only be greater than PAGE_SIZE if we are
** confident the drivers really only touch the next physical
** page iff that driver instance owns it.
*/
#define IOVP_SIZE	PAGE_SIZE
#define IOVP_SHIFT	PAGE_SHIFT
#define IOVP_MASK	PAGE_MASK

#define SBA_PERF_CFG	0x708	/* Performance Counter stuff */
#define SBA_PERF_MASK1	0x718
#define SBA_PERF_MASK2	0x730


/*
** Offsets into PCI Performance Counters (functions 12 and 13)
** Controlled by PERF registers in function 2 & 3 respectively.
*/
#define SBA_PERF_CNT1	0x200
#define SBA_PERF_CNT2	0x208
#define SBA_PERF_CNT3	0x210


struct ioc {
	char    *ioc_hpa;	/* I/O MMU base address */
	char	*res_map;	/* resource map, bit == pdir entry */
	u64	*pdir_base;	/* physical base address */

	unsigned long	*res_hint;	/* next available IOVP - circular search */
	unsigned int	res_bitshift;	/* from the LEFT! */
	unsigned int	res_size;	/* size of resource map in bytes */
	unsigned int	hint_shift_pdir;
	spinlock_t	res_lock;
	unsigned long	hint_mask_pdir;		/* bits used for DMA hints */
#ifdef DELAYED_RESOURCE_CNT
	dma_addr_t res_delay[DELAYED_RESOURCE_CNT];
#endif

#ifdef CONFIG_PROC_FS
#define SBA_SEARCH_SAMPLE	0x100
	unsigned long avg_search[SBA_SEARCH_SAMPLE];
	unsigned long avg_idx;	/* current index into avg_search */
	unsigned long used_pages;
	unsigned long msingle_calls;
	unsigned long msingle_pages;
	unsigned long msg_calls;
	unsigned long msg_pages;
	unsigned long usingle_calls;
	unsigned long usingle_pages;
	unsigned long usg_calls;
	unsigned long usg_pages;
#endif

	/* STUFF We don't need in performance path */
	unsigned int	pdir_size;	/* in bytes, determined by IOV Space size */
	unsigned long	ibase;		/* pdir IOV Space base - shared w/lba_pci */
	unsigned long	imask;		/* pdir IOV Space mask - shared w/lba_pci */
};

struct sba_device {
	struct sba_device	*next;	/* list of LBA's in system */
	struct hp_device	*iodc;	/* data about dev from firmware */
	char			*sba_hpa; /* base address */
	spinlock_t		sba_lock;
	unsigned int			flags;  /* state/functionality enabled */
	unsigned int			hw_rev;  /* HW revision of chip */

	unsigned int			num_ioc;  /* number of on-board IOC's */
	struct ioc		ioc[MAX_IOC];
};


static struct sba_device *sba_list;
static int sba_count;

/* Ratio of Host MEM to IOV Space size */
static unsigned long sba_mem_ratio = 4;

/* Looks nice and keeps the compiler happy */
#define SBA_DEV(d) ((struct sba_device *) (d))


#define ROUNDUP(x,y) ((x + ((y)-1)) & ~((y)-1))


/************************************
** SBA register read and write support
**
** BE WARNED: register writes are posted.
**  (ie follow writes which must reach HW with a read)
*/
#define READ_U8(addr)  gsc_readb(addr)
#define READ_U16(addr) gsc_readw((u16 *) (addr))
#define READ_U32(addr) gsc_readl((u32 *) (addr))
#define WRITE_U8(value, addr) gsc_writeb(value, addr)
#define WRITE_U16(value, addr) gsc_writew(value, (u16 *) (addr))
#define WRITE_U32(value, addr) gsc_writel(value, (u32 *) (addr))

#define READ_REG8(addr)  gsc_readb(addr)
#define READ_REG16(addr) le16_to_cpu(gsc_readw((u16 *) (addr)))
#define READ_REG32(addr) le32_to_cpu(gsc_readl((u32 *) (addr)))
#define READ_REG64(addr) le64_to_cpu(gsc_readq((u64 *) (addr)))
#define WRITE_REG8(value, addr) gsc_writeb(value, addr)
#define WRITE_REG16(value, addr) gsc_writew(cpu_to_le16(value), (u16 *) (addr))
#define WRITE_REG32(value, addr) gsc_writel(cpu_to_le32(value), (u32 *) (addr))
#define WRITE_REG64(value, addr) gsc_writeq(cpu_to_le64(value), (u64 *) (addr))

#ifdef DEBUG_SBA_INIT

static void
sba_dump_ranges(char *hpa)
{
	printk("SBA at 0x%p\n", hpa);
	printk("IOS_DIST_BASE   : %08x %08x\n",
			READ_REG32(hpa+IOS_DIST_BASE+4),
			READ_REG32(hpa+IOS_DIST_BASE));
	printk("IOS_DIST_MASK   : %08x %08x\n",
			READ_REG32(hpa+IOS_DIST_MASK+4),
			READ_REG32(hpa+IOS_DIST_MASK));
	printk("IOS_DIST_ROUTE  : %08x %08x\n",
			READ_REG32(hpa+IOS_DIST_ROUTE+4),
			READ_REG32(hpa+IOS_DIST_ROUTE));
	printk("\n");
	printk("IOS_DIRECT_BASE : %08x %08x\n",
			READ_REG32(hpa+IOS_DIRECT_BASE+4),
			READ_REG32(hpa+IOS_DIRECT_BASE));
	printk("IOS_DIRECT_MASK : %08x %08x\n",
			READ_REG32(hpa+IOS_DIRECT_MASK+4),
			READ_REG32(hpa+IOS_DIRECT_MASK));
	printk("IOS_DIRECT_ROUTE: %08x %08x\n",
			READ_REG32(hpa+IOS_DIRECT_ROUTE+4),
			READ_REG32(hpa+IOS_DIRECT_ROUTE));
}

static void
sba_dump_tlb(char *hpa)
{
	printk("IO TLB at 0x%p\n", hpa);
	printk("IOC_IBASE   : %08x %08x\n",
			READ_REG32(hpa+IOC_IBASE+4),
			READ_REG32(hpa+IOC_IBASE));
	printk("IOC_IMASK   : %08x %08x\n",
			READ_REG32(hpa+IOC_IMASK+4),
			READ_REG32(hpa+IOC_IMASK));
	printk("IOC_TCNFG   : %08x %08x\n",
			READ_REG32(hpa+IOC_TCNFG+4),
			READ_REG32(hpa+IOC_TCNFG));
	printk("IOC_PDIR_BASE: %08x %08x\n",
			READ_REG32(hpa+IOC_PDIR_BASE+4),
			READ_REG32(hpa+IOC_PDIR_BASE));
	printk("\n");
}
#endif


#ifdef ASSERT_PDIR_SANITY

static void
sba_dump_pdir_entry(struct ioc *ioc, char *msg, uint pide)
{
	/* start printing from lowest pde in rval */
	u64 *ptr = &(ioc->pdir_base[pide & (~0U * BITS_PER_LONG)]);
	unsigned long *rptr = (unsigned long *) &(ioc->res_map[(pide >>3) & ~(sizeof(unsigned long) - 1)]);
	uint rcnt;

	printk("SBA: %s rp %p bit %d rval 0x%lx\n",
		 msg,
		 rptr, pide & (BITS_PER_LONG - 1), *rptr);

	rcnt = 0;
	while (rcnt < BITS_PER_LONG) {
		printk("%s %2d %p %016Lx\n",
			(rcnt == (pide & (BITS_PER_LONG - 1)))
				? "    -->" : "       ",
			rcnt, ptr, *ptr );
		rcnt++;
		ptr++;
	}
	printk(msg);
}


/* Verify the resource map and pdir state is consistent */
static int
sba_check_pdir(struct ioc *ioc, char *msg)
{
	u32 *rptr_end = (u32 *) &(ioc->res_map[ioc->res_size]);
	u32 *rptr = (u32 *) ioc->res_map;	/* resource map ptr */
	u64 *pptr = ioc->pdir_base;	/* pdir ptr */
	uint pide = 0;

	while (rptr < rptr_end) {
		u32 rval = *rptr;
		int rcnt = 32;	/* number of bits we might check */

		while (rcnt) {
			/* Get last byte and highest bit from that */
			u32 pde = ((u32) (((char *)pptr)[7])) << 24;
			if ((rval ^ pde) & 0x80000000)
			{
				/*
				** BUMMER!  -- res_map != pdir --
				** Dump rval and matching pdir entries
				*/
				sba_dump_pdir_entry(ioc, msg, pide);
				return(1);
			}
			rcnt--;
			rval <<= 1;	/* try the next bit */
			pptr++;
			pide++;
		}
		rptr++;	/* look at next word of res_map */
	}
	/* It'd be nice if we always got here :^) */
	return 0;
}


static void
sba_dump_sg( struct ioc *ioc, struct scatterlist *startsg, int nents)
{
	while (nents-- > 0) {
		printk(" %d : %08lx/%05x %p/%05x\n",
				nents,
				(unsigned long) sg_dma_address(startsg),
				sg_dma_len(startsg),
				startsg->address, startsg->length);