palinfo.c

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/*
 * palinfo.c
 *
 * Prints processor specific information reported by PAL.
 * This code is based on specification of PAL as of the
 * Intel IA-64 Architecture Software Developer's Manual v1.0.
 *
 * 
 * Copyright (C) 2000 Hewlett-Packard Co
 * Copyright (C) 2000 Stephane Eranian <[e-mail]>
 * 
 * 05/26/2000	S.Eranian	initial release
 * 08/21/2000	S.Eranian	updated to July 2000 PAL specs
 *
 * ISSUES:
 *	- as of 2.2.9/2.2.12, the following values are still wrong
 *		PAL_VM_SUMMARY: key & rid sizes
 */
#include <linux/config.h>
#include <linux/types.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/proc_fs.h>
#include <linux/mm.h>
#include <linux/module.h>
#if defined(MODVERSIONS)
#include <linux/modversions.h>
#endif

#include <asm/pal.h>
#include <asm/sal.h>
#include <asm/efi.h>
#include <asm/page.h>
#include <asm/processor.h>
#ifdef CONFIG_SMP
#include <linux/smp.h>
#endif

MODULE_AUTHOR("Stephane Eranian <[e-mail]>");
MODULE_DESCRIPTION("/proc interface to IA-64 PAL");

/*
 * Hope to get rid of this one in a near future
*/
#define IA64_PAL_VERSION_BUG		1

#define PALINFO_VERSION "0.3"

#ifdef CONFIG_SMP
#define cpu_is_online(i) (cpu_online_map & (1UL << i))
#else
#define cpu_is_online(i)	1
#endif

typedef int (*palinfo_func_t)(char*);

typedef struct {
	const char		*name;		/* name of the proc entry */
	palinfo_func_t		proc_read;	/* function to call for reading */
	struct proc_dir_entry	*entry;		/* registered entry (removal) */
} palinfo_entry_t;


/*
 *  A bunch of string array to get pretty printing
 */

static char *cache_types[] = {
	"",			/* not used */
	"Instruction",
	"Data",
	"Data/Instruction"	/* unified */
};

static const char *cache_mattrib[]={
	"WriteThrough",
	"WriteBack",
	"",		/* reserved */
	""		/* reserved */
};

static const char *cache_st_hints[]={
	"Temporal, level 1",
	"Reserved",
	"Reserved",
	"Non-temporal, all levels",
	"Reserved",
	"Reserved",
	"Reserved",	
	"Reserved"
};

static const char *cache_ld_hints[]={
	"Temporal, level 1",
	"Non-temporal, level 1",
	"Reserved",
	"Non-temporal, all levels",
	"Reserved",
	"Reserved",
	"Reserved",	
	"Reserved"
};

static const char *rse_hints[]={
	"enforced lazy",
	"eager stores",
	"eager loads",
	"eager loads and stores"
};

#define RSE_HINTS_COUNT (sizeof(rse_hints)/sizeof(const char *))

/*
 * The current revision of the Volume 2 (July 2000) of 
 * IA-64 Architecture Software Developer's Manual is wrong.
 * Table 4-10 has invalid information concerning the ma field:
 * Correct table is:
 *      bit 0 - 001 - UC
 *      bit 4 - 100 - UC
 *      bit 5 - 101 - UCE
 *      bit 6 - 110 - WC
 *      bit 7 - 111 - NatPage 
 */
static const char *mem_attrib[]={
	"Write Back (WB)",		/* 000 */
	"Uncacheable (UC)",		/* 001 */
	"Reserved",			/* 010 */
	"Reserved",			/* 011 */
	"Uncacheable (UC)",		/* 100 */
	"Uncacheable Exported (UCE)",	/* 101 */
	"Write Coalescing (WC)",	/* 110 */
	"NaTPage"			/* 111 */
};

/*
 * Take a 64bit vector and produces a string such that
 * if bit n is set then 2^n in clear text is generated. The adjustment
 * to the right unit is also done.
 *
 * Input:
 *	- a pointer to a buffer to hold the string
 * 	- a 64-bit vector
 * Ouput:
 *	- a pointer to the end of the buffer
 *
 */
static char *
bitvector_process(char *p, u64 vector)
{
	int i,j;
	const char *units[]={ "", "K", "M", "G", "T" };

	for (i=0, j=0; i < 64; i++ , j=i/10) {
		if (vector & 0x1) {
			p += sprintf(p, "%d%s ", 1 << (i-j*10), units[j]);
		}
		vector >>= 1;
	}
	return p;
}

/*
 * Take a 64bit vector and produces a string such that
 * if bit n is set then register n is present. The function
 * takes into account consecutive registers and prints out ranges.
 *
 * Input:
 *	- a pointer to a buffer to hold the string
 * 	- a 64-bit vector
 * Ouput:
 *	- a pointer to the end of the buffer
 *
 */
static char *
bitregister_process(char *p, u64 *reg_info, int max)
{
	int i, begin, skip = 0;
	u64 value = reg_info[0];

	value >>= i = begin = ffs(value) - 1;

	for(; i < max; i++ ) {

		if (i != 0 && (i%64) == 0) value = *++reg_info;

		if ((value & 0x1) == 0 && skip == 0) {
			if (begin  <= i - 2) 
				p += sprintf(p, "%d-%d ", begin, i-1);
			else
				p += sprintf(p, "%d ", i-1);
			skip  = 1;
			begin = -1;
		} else if ((value & 0x1) && skip == 1) {
			skip = 0;
			begin = i;
		}
		value >>=1;
	}
	if (begin > -1) {
		if (begin < 127) 
			p += sprintf(p, "%d-127", begin);
		else
			p += sprintf(p, "127");
	}

	return p;
}

static int
power_info(char *page)
{
	s64 status;
	char *p = page;
	u64 halt_info_buffer[8];
	pal_power_mgmt_info_u_t *halt_info =(pal_power_mgmt_info_u_t *)halt_info_buffer;
	int i;

	status = ia64_pal_halt_info(halt_info);
	if (status != 0) return 0;

	for (i=0; i < 8 ; i++ ) {
		if (halt_info[i].pal_power_mgmt_info_s.im == 1) {
			p += sprintf(p,	"Power level %d:\n" \
					"\tentry_latency       : %d cycles\n" \
				 	"\texit_latency        : %d cycles\n" \
					"\tpower consumption   : %d mW\n" \
					"\tCache+TLB coherency : %s\n", i,
				halt_info[i].pal_power_mgmt_info_s.entry_latency,
				halt_info[i].pal_power_mgmt_info_s.exit_latency,
				halt_info[i].pal_power_mgmt_info_s.power_consumption,
				halt_info[i].pal_power_mgmt_info_s.co ? "Yes" : "No");
		} else {
			p += sprintf(p,"Power level %d: not implemented\n",i);
		}
	}
	return p - page;
}

static int 
cache_info(char *page)
{
	char *p = page;
	u64 levels, unique_caches;
	pal_cache_config_info_t cci;
	int i,j, k;
	s64 status;

	if ((status=ia64_pal_cache_summary(&levels, &unique_caches)) != 0) {
			printk("ia64_pal_cache_summary=%ld\n", status);
			return 0;
	}

	p += sprintf(p, "Cache levels  : %ld\n" \
			"Unique caches : %ld\n\n",
			levels,
			unique_caches);

	for (i=0; i < levels; i++) {

		for (j=2; j >0 ; j--) {

			/* even without unification some level may not be present */
			if ((status=ia64_pal_cache_config_info(i,j, &cci)) != 0) {
				continue;
			}
			p += sprintf(p, "%s Cache level %d:\n" \
					"\tSize           : %ld bytes\n" \
					"\tAttributes     : ",
					cache_types[j+cci.pcci_unified], i+1,
					cci.pcci_cache_size);

			if (cci.pcci_unified) p += sprintf(p, "Unified ");

			p += sprintf(p, "%s\n", cache_mattrib[cci.pcci_cache_attr]);

			p += sprintf(p, "\tAssociativity  : %d\n" \
					"\tLine size      : %d bytes\n" \
					"\tStride         : %d bytes\n",
					cci.pcci_assoc,
					1<<cci.pcci_line_size,
					1<<cci.pcci_stride);
			if (j == 1)
				p += sprintf(p, "\tStore latency  : N/A\n");
			else
				p += sprintf(p, "\tStore latency  : %d cycle(s)\n",
						cci.pcci_st_latency);

			p += sprintf(p, "\tLoad latency   : %d cycle(s)\n" \
					"\tStore hints    : ",
					cci.pcci_ld_latency);

			for(k=0; k < 8; k++ ) {
				if ( cci.pcci_st_hints & 0x1) p += sprintf(p, "[%s]", cache_st_hints[k]);
				cci.pcci_st_hints >>=1; 
			}
			p += sprintf(p, "\n\tLoad hints     : ");

			for(k=0; k < 8; k++ ) {
				if ( cci.pcci_ld_hints & 0x1) p += sprintf(p, "[%s]", cache_ld_hints[k]);
				cci.pcci_ld_hints >>=1; 
			}
			p += sprintf(p, "\n\tAlias boundary : %d byte(s)\n" \
					"\tTag LSB        : %d\n" \
					"\tTag MSB        : %d\n",
					1<<cci.pcci_alias_boundary,
					cci.pcci_tag_lsb,
					cci.pcci_tag_msb);

			/* when unified, data(j=2) is enough */
			if (cci.pcci_unified) break;
		}
	}
	return p - page;
}


static int
vm_info(char *page)
{
	char *p = page;
	u64 tr_pages =0, vw_pages=0, tc_pages;
	u64 attrib;
	pal_vm_info_1_u_t vm_info_1;
	pal_vm_info_2_u_t vm_info_2;
	pal_tc_info_u_t	tc_info;
	ia64_ptce_info_t ptce;
	int i, j;
	s64 status;

	if ((status=ia64_pal_vm_summary(&vm_info_1, &vm_info_2)) !=0) {
		printk("ia64_pal_vm_summary=%ld\n", status);
		return 0;
	}


	p += sprintf(p, "Physical Address Space         : %d bits\n" \
			"Virtual Address Space          : %d bits\n" \
			"Protection Key Registers(PKR)  : %d\n" \
			"Implemented bits in PKR.key    : %d\n" \
			"Hash Tag ID                    : 0x%x\n" \
			"Size of RR.rid                 : %d\n",
			vm_info_1.pal_vm_info_1_s.phys_add_size,
			vm_info_2.pal_vm_info_2_s.impl_va_msb+1,
			vm_info_1.pal_vm_info_1_s.max_pkr+1,
			vm_info_1.pal_vm_info_1_s.key_size,
			vm_info_1.pal_vm_info_1_s.hash_tag_id,
			vm_info_2.pal_vm_info_2_s.rid_size);

	if (ia64_pal_mem_attrib(&attrib) != 0) return 0;

	p += sprintf(p, "Supported memory attributes    : %s\n", mem_attrib[attrib&0x7]);

	if ((status=ia64_pal_vm_page_size(&tr_pages, &vw_pages)) !=0) {
		printk("ia64_pal_vm_page_size=%ld\n", status);
		return 0;
	}

	p += sprintf(p, "\nTLB walker                     : %s implemented\n" \
			"Number of DTR                  : %d\n" \
			"Number of ITR                  : %d\n" \
			"TLB insertable page sizes      : ",
			vm_info_1.pal_vm_info_1_s.vw ? "\b":"not",
			vm_info_1.pal_vm_info_1_s.max_dtr_entry+1,
			vm_info_1.pal_vm_info_1_s.max_itr_entry+1);


	p = bitvector_process(p, tr_pages);

	p += sprintf(p, "\nTLB purgeable page sizes       : ");

	p = bitvector_process(p, vw_pages);

	if ((status=ia64_get_ptce(&ptce)) != 0) {
		printk("ia64_get_ptce=%ld\n",status);
		return 0;
	}

	p += sprintf(p, "\nPurge base address             : 0x%016lx\n" \
			"Purge outer loop count         : %d\n" \
			"Purge inner loop count         : %d\n" \
			"Purge outer loop stride        : %d\n" \
			"Purge inner loop stride        : %d\n",
			ptce.base,
			ptce.count[0],
			ptce.count[1],
			ptce.stride[0],
			ptce.stride[1]);

	p += sprintf(p, "TC Levels                      : %d\n" \
			"Unique TC(s)                   : %d\n", 
			vm_info_1.pal_vm_info_1_s.num_tc_levels,
			vm_info_1.pal_vm_info_1_s.max_unique_tcs);

	for(i=0; i < vm_info_1.pal_vm_info_1_s.num_tc_levels; i++) {
		for (j=2; j>0 ; j--) {
			tc_pages = 0; /* just in case */

		
			/* even without unification, some levels may not be present */
			if ((status=ia64_pal_vm_info(i,j, &tc_info, &tc_pages)) != 0) {
				continue;
			}

			p += sprintf(p, "\n%s Translation Cache Level %d:\n" \
					"\tHash sets           : %d\n" \
					"\tAssociativity       : %d\n" \
					"\tNumber of entries   : %d\n" \
					"\tFlags               : ",
					cache_types[j+tc_info.tc_unified], i+1,
					tc_info.tc_num_sets,
					tc_info.tc_associativity,
					tc_info.tc_num_entries);

			if (tc_info.tc_pf) p += sprintf(p, "PreferredPageSizeOptimized ");
			if (tc_info.tc_unified) p += sprintf(p, "Unified ");
			if (tc_info.tc_reduce_tr) p += sprintf(p, "TCReduction");

			p += sprintf(p, "\n\tSupported page sizes: ");

			p = bitvector_process(p, tc_pages);

			/* when unified date (j=2) is enough */
			if (tc_info.tc_unified) break;
		}
	}
	p += sprintf(p, "\n");

	return p - page;	
}


static int
register_info(char *page)
{
	char *p = page;
	u64 reg_info[2];
	u64 info;
	u64 phys_stacked;
	pal_hints_u_t hints;
	u64 iregs, dregs;
	char *info_type[]={
		"Implemented AR(s)",
		"AR(s) with read side-effects",
		"Implemented CR(s)",
		"CR(s) with read side-effects",
	};

	for(info=0; info < 4; info++) {

		if (ia64_pal_register_info(info, &reg_info[0], &reg_info[1]) != 0) return 0;

	 	p += sprintf(p, "%-32s : ", info_type[info]);

		p = bitregister_process(p, reg_info, 128);

		p += sprintf(p, "\n");
	}

	if (ia64_pal_rse_info(&phys_stacked, &hints) != 0) return 0;

	p += sprintf(p, "RSE stacked physical registers   : %ld\n" \
			"RSE load/store hints             : %ld (%s)\n",
			phys_stacked,
			hints.ph_data, 
		     	hints.ph_data < RSE_HINTS_COUNT ? rse_hints[hints.ph_data]: "(\?\?)");

	if (ia64_pal_debug_info(&iregs, &dregs)) return 0;

	p += sprintf(p, "Instruction debug register pairs : %ld\n" \
			"Data debug register pairs        : %ld\n",
			iregs, dregs);

	return p - page;
}

static const char *proc_features[]={
	NULL,NULL,NULL,NULL,NULL,NULL,NULL,NULL,NULL,
	NULL,NULL,NULL,NULL,NULL,NULL,NULL, NULL,NULL,
	NULL,NULL,NULL,NULL,NULL,NULL,NULL,NULL,NULL,
	NULL,NULL,NULL,NULL,NULL, NULL,NULL,NULL,NULL,
	NULL,NULL,NULL,NULL,NULL,
	"XIP,XPSR,XFS implemented",
	"XR1-XR3 implemented",
	"Disable dynamic predicate prediction",
	"Disable processor physical number",
	"Disable dynamic data cache prefetch",
	"Disable dynamic inst cache prefetch",
	"Disable dynamic branch prediction",
	NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
	"Disable BINIT on processor time-out",
	"Disable dynamic power management (DPM)",
	"Disable coherency", 
	"Disable cache", 
	"Enable CMCI promotion",
	"Enable MCA to BINIT promotion",
	"Enable MCA promotion",
	"Enable BEER promotion"
};

	
static int
processor_info(char *page)
{
	char *p = page;