pci_bus_cvlink.c

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			device_dev->resource[idx].end = 
				device_dev->resource[idx].start + size;

			/*
			 * Adjust the addresses to go to the SWIZZLE ..
			 */
			device_dev->resource[idx].start = 
				device_dev->resource[idx].start & 0xfffff7ffffffffff;
			device_dev->resource[idx].end = 
				device_dev->resource[idx].end & 0xfffff7ffffffffff;
			printk(" to 0x%lx\n", device_dev->resource[idx].start);
res = 0;
res = pciio_config_get(vhdl, (unsigned) PCI_BASE_ADDRESS_0 + idx, 4);
printk("After pciio_pio_addr Base address %d = 0x%lx\n", idx, res);

			if (device_dev->resource[idx].flags & IORESOURCE_IO)
				cmd |= PCI_COMMAND_IO;
			else if (device_dev->resource[idx].flags & IORESOURCE_MEM)
				cmd |= PCI_COMMAND_MEMORY;
		}
		/*
		 * Now handle the ROM resource ..
		 */
		size = device_dev->resource[PCI_ROM_RESOURCE].end -
			device_dev->resource[PCI_ROM_RESOURCE].start;
		printk(" Changing device %d:%d ROM resource start address from 0x%lx", 
			PCI_SLOT(device_dev->devfn),PCI_FUNC(device_dev->devfn),
			device_dev->resource[PCI_ROM_RESOURCE].start);
		device_dev->resource[PCI_ROM_RESOURCE].start =
			(unsigned long) pciio_pio_addr(vhdl, 0, PCIIO_SPACE_ROM, 0, 
				size, 0, PCIIO_BYTE_STREAM);
		device_dev->resource[PCI_ROM_RESOURCE].end =
			device_dev->resource[PCI_ROM_RESOURCE].start + size;

                /*
                 * go through synergy swizzled space
                 */
		device_dev->resource[PCI_ROM_RESOURCE].start &= 0xfffff7ffffffffffUL;
		device_dev->resource[PCI_ROM_RESOURCE].end   &= 0xfffff7ffffffffffUL;

		/*
		 * Update the Command Word on the Card.
		 */
		cmd |= PCI_COMMAND_MASTER; /* If the device doesn't support */
					   /* bit gets dropped .. no harm */
		pci_write_config_word(device_dev, PCI_COMMAND, cmd);

		printk("  to 0x%lx\n", device_dev->resource[PCI_ROM_RESOURCE].start);

		/*
		 * Set the irq correctly.
		 * Bits 7:3 = slot
		 * Bits 2:0 = function
		 *
		 * In the IRQ we will have:
		 *	Bits 24:16 = bus number
		 *	Bits 15:8 = slot|func number
		 */
		irq = 0;
		irq = (irq | (device_dev->devfn << 8));
		irq = (irq | ( (device_dev->bus->number & 0xff) << 16) );
		device_dev->irq = irq;
printk("sn1_pci_fixup: slot= %d  fn= %d  vendor= 0x%x  device= 0x%x  irq= 0x%x\n",
PCI_SLOT(device_dev->devfn),PCI_FUNC(device_dev->devfn),device_dev->vendor,
device_dev->device, device_dev->irq);

	}
#endif	/* REAL_HARDWARE */
#if 0

{
        devfs_handle_t  bridge_vhdl = pci_bus_to_vertex(0);
        pcibr_soft_t    pcibr_soft = (pcibr_soft_t) hwgraph_fastinfo_get(bridge_vhdl);
        bridge_t        *bridge = pcibr_soft->bs_base;

printk("After Changing PIO Map Address:\n");
        printk("pci_fixup_ioc3: Before devreg fixup\n");
        printk("pci_fixup_ioc3: Devreg 0 0x%x\n", bridge->b_device[0].reg);
        printk("pci_fixup_ioc3: Devreg 1 0x%x\n", bridge->b_device[1].reg);
        printk("pci_fixup_ioc3: Devreg 2 0x%x\n", bridge->b_device[2].reg);
        printk("pci_fixup_ioc3: Devreg 3 0x%x\n", bridge->b_device[3].reg);
        printk("pci_fixup_ioc3: Devreg 4 0x%x\n", bridge->b_device[4].reg);
        printk("pci_fixup_ioc3: Devreg 5 0x%x\n", bridge->b_device[5].reg);
        printk("pci_fixup_ioc3: Devreg 6 0x%x\n", bridge->b_device[6].reg);
        printk("pci_fixup_ioc3: Devreg 7 0x%x\n", bridge->b_device[7].reg);
}
#endif

}

/*
 * pci_bus_map_create() - Called by pci_bus_to_hcl_cvlink() to finish the job.
 */
static int 
pci_bus_map_create(devfs_handle_t xtalk)
{

	devfs_handle_t master_node_vertex = NULL;
	devfs_handle_t xwidget = NULL;
	devfs_handle_t pci_bus = NULL;
	hubinfo_t hubinfo = NULL;
	xwidgetnum_t widgetnum;
	char pathname[128];
	graph_error_t rv;

	/*
	 * Loop throught this vertex and get the Xwidgets ..
	 */
	for (widgetnum = HUB_WIDGET_ID_MIN; widgetnum <= HUB_WIDGET_ID_MAX; widgetnum++) {
		sprintf(pathname, "%d", widgetnum);
		xwidget = NULL;
		
		rv = hwgraph_traverse(xtalk, pathname, &xwidget);
		if ( (rv != GRAPH_SUCCESS) ) {
			if (!xwidget)
				continue;
		}

		sprintf(pathname, "%d/"EDGE_LBL_PCI, widgetnum);
		pci_bus = NULL;
		if (hwgraph_traverse(xtalk, pathname, &pci_bus) != GRAPH_SUCCESS)
			if (!pci_bus)
				continue;

		/*
		 * Assign the correct bus number and also the nasid of this 
		 * pci Xwidget.
		 * 
		 * Should not be any race here ...
		 */
		num_bridges++;
		busnum_to_xwidget[num_bridges - 1] = xwidget;

		/*
		 * Get the master node and from there get the NASID.
		 */
		master_node_vertex = device_master_get(xwidget);
		if (!master_node_vertex) {
			printk(" **** pci_bus_map_create: Unable to get .master for vertex 0x%p **** \n", xwidget);
		}
	
		hubinfo_get(master_node_vertex, &hubinfo);
		if (!hubinfo) {
			printk(" **** pci_bus_map_create: Unable to get hubinfo for master node vertex 0x%p ****\n", master_node_vertex);
			return(1);
		} else {
			busnum_to_nid[num_bridges - 1] = hubinfo->h_nasid;
		}

		printk("pci_bus_map_create: Found Hub nasid %d PCI Xwidget 0x%p  widgetnum= %d\n", hubinfo->h_nasid, xwidget, widgetnum);
	}

        return(0);
}

/*
 * pci_bus_to_hcl_cvlink() - This routine is called after SGI IO Infrastructure   
 *      initialization has completed to set up the mappings between Xbridge
 *      and logical pci bus numbers.  We also set up the NASID for each of these
 *      xbridges.
 *
 *      Must be called before pci_init() is invoked.
 */
int
pci_bus_to_hcl_cvlink(void) 
{

	devfs_handle_t devfs_hdl = NULL;
	devfs_handle_t module_comp = NULL;
	devfs_handle_t node = NULL;
	devfs_handle_t xtalk = NULL;
	graph_vertex_place_t placeptr = EDGE_PLACE_WANT_REAL_EDGES;
	int rv = 0;
	char name[256];

	/*
	 * Iterate throught each xtalk links in the system ..
	 * /hw/module/001c01/node/xtalk/ 8|9|10|11|12|13|14|15 
	 *
	 * /hw/module/001c01/node/xtalk/15 -> /hw/module/001c01/Ibrick/xtalk/15
	 *
	 * What if it is not pci?
	 */
	devfs_hdl = hwgraph_path_to_vertex("/dev/hw/module");

	/*
	 * Loop throught this directory "/devfs/hw/module/" and get each 
	 * of it's entry.
	 */
	while (1) {
	
		/* Get vertex of component /dev/hw/<module_number> */
		memset((char *)name, '0', 256);
		module_comp = NULL;
		rv = hwgraph_edge_get_next(devfs_hdl, (char *)name, &module_comp, (uint *)&placeptr);
		if ((rv == 0) && (module_comp)) {
			/* Found a valid entry */
			node = NULL;
			rv = hwgraph_edge_get(module_comp, "node", &node);

		} else {
			printk("pci_bus_to_hcl_cvlink: No more Module Component.\n");
			return(0);
		}

		if ( (rv != 0) || (!node) ){
			printk("pci_bus_to_hcl_cvlink: Module Component does not have node vertex.\n");
			continue;
		} else {
			xtalk = NULL;
			rv = hwgraph_edge_get(node, "xtalk", &xtalk);
			if ( (rv != 0) || (xtalk == NULL) ){
				printk("pci_bus_to_hcl_cvlink: Node has no xtalk vertex.\n");
				continue;
			}
		}

		printk("pci_bus_to_hcl_cvlink: Found Module %s node vertex = 0x%p xtalk vertex = 0x%p\n", name, node, xtalk);
		/*
		 * Call routine to get the existing PCI Xwidget and create
		 * the convenience link from "/devfs/hw/pci_bus/.."
		 */
		pci_bus_map_create(xtalk);
	}

	return(0);
}

/*
 * sgi_pci_intr_support -
 */
int
sgi_pci_intr_support (unsigned int requested_irq, device_desc_t *dev_desc,
	devfs_handle_t *bus_vertex, pciio_intr_line_t *lines,
	devfs_handle_t *device_vertex)

{

	unsigned int bus;
	unsigned int devfn;
	struct pci_dev *pci_dev;
	unsigned char intr_pin = 0;
	struct sn1_widget_sysdata *widget_sysdata;
	struct sn1_device_sysdata *device_sysdata;

	printk("sgi_pci_intr_support: Called with requested_irq 0x%x\n", requested_irq);

	if (!dev_desc || !bus_vertex || !device_vertex) {
		printk("sgi_pci_intr_support: Invalid parameter dev_desc 0x%p, bus_vertex 0x%p, device_vertex 0x%p\n", dev_desc, bus_vertex, device_vertex);
		return(-1);
	}

	devfn = (requested_irq >> 8) & 0xff;
	bus = (requested_irq >> 16) & 0xffff;
	pci_dev = pci_find_slot(bus, devfn);
	widget_sysdata = (struct sn1_widget_sysdata *)pci_dev->bus->sysdata;
	*bus_vertex = widget_sysdata->vhdl;
	device_sysdata = (struct sn1_device_sysdata *)pci_dev->sysdata;
	*device_vertex = device_sysdata->vhdl;
#if 0
	{
		int pos;
		char dname[256];
		pos = devfs_generate_path(*device_vertex, dname, 256);
		printk("%s : path= %s pos %d\n", __FUNCTION__, &dname[pos], pos);
	}
#endif /* BRINGUP */


	/*
	 * Get the Interrupt PIN.
	 */
	pci_read_config_byte(pci_dev, PCI_INTERRUPT_PIN, &intr_pin);
	*lines = (pciio_intr_line_t)intr_pin;

#ifdef BRINGUP
	/*
	 * ioc3 can't decode the PCI_INTERRUPT_PIN field of its config
	 * space so we have to set it here
	 */
	if (pci_dev->vendor == PCI_VENDOR_ID_SGI &&
	    pci_dev->device == PCI_DEVICE_ID_SGI_IOC3 ) {
		*lines = 1;
		printk("%s : IOC3 HACK: lines= %d\n", __FUNCTION__, *lines);
	}
#endif /* BRINGUP */

	/* Not supported currently */
	*dev_desc = NULL;

	printk("sgi_pci_intr_support: Device Descriptor 0x%p, Bus Vertex 0x%p, Interrupt Pins 0x%x, Device Vertex 0x%p\n", *dev_desc, *bus_vertex, *lines, *device_vertex);

	return(0);

}