📄 protect.rpt
字号:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information:c:\software\project_beijing\cpld_v1.1\pwm_verilog hdl_v1.1\protect.rpt
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** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
(41) 17 B SOFT t 0 0 0 0 1 1 0 |lpm_add_sub:130|addcore:adder|addcore:adder0|result_node2
(32) 25 B TFFE + t 1 0 0 0 4 0 5 counter3 (:59)
(33) 24 B DFFE + t 0 0 0 0 4 0 5 counter2 (:60)
(29) 27 B DFFE + t 0 0 0 0 4 0 5 counter1 (:61)
(34) 23 B DFFE + t 0 0 0 0 4 0 5 counter0 (:62)
(36) 22 B DFFE + t 0 0 0 0 4 0 1 divi_cp (:69)
(37) 21 B DFFE + t 0 0 0 0 1 0 2 clk (:71)
(38) 20 B DFFE t 0 0 0 0 2 1 0 q1 (:76)
(39) 19 B DFFE t 0 0 0 1 1 1 2 q0 (:77)
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information:c:\software\project_beijing\cpld_v1.1\pwm_verilog hdl_v1.1\protect.rpt
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** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+------------------- LC18 guarder_out
| +----------------- LC17 |lpm_add_sub:130|addcore:adder|addcore:adder0|result_node2
| | +--------------- LC25 counter3
| | | +------------- LC24 counter2
| | | | +----------- LC27 counter1
| | | | | +--------- LC23 counter0
| | | | | | +------- LC22 divi_cp
| | | | | | | +----- LC21 clk
| | | | | | | | +--- LC20 q1
| | | | | | | | | +- LC19 q0
| | | | | | | | | |
| | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | | A B | Logic cells that feed LAB 'B':
LC17 -> * - - - - - - - - - | - * | <-- |lpm_add_sub:130|addcore:adder|addcore:adder0|result_node2
LC25 -> - - * * * * * - - - | - * | <-- counter3
LC24 -> - - * * * * * - - - | - * | <-- counter2
LC27 -> - - * * * * * - - - | - * | <-- counter1
LC23 -> - - * * * * * - - - | - * | <-- counter0
LC22 -> - - - - - - - * - - | - * | <-- divi_cp
LC21 -> - - - - - - - - * * | - * | <-- clk
LC20 -> * - - - - - - - - - | - * | <-- q1
LC19 -> * * - - - - - - * - | - * | <-- q0
Pin
43 -> - - - - - - - - - - | - - | <-- cp
5 -> - - - - - - - - - * | - * | <-- curr_in
6 -> * - - - - - - - - - | - * | <-- heat_in
4 -> * - - - - - - - - - | - * | <-- vol_in
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information:c:\software\project_beijing\cpld_v1.1\pwm_verilog hdl_v1.1\protect.rpt
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** EQUATIONS **
cp : INPUT;
curr_in : INPUT;
heat_in : INPUT;
vol_in : INPUT;
-- Node name is ':71' = 'clk'
-- Equation name is 'clk', location is LC021, type is buried.
clk = DFFE( divi_cp $ GND, GLOBAL( cp), VCC, VCC, VCC);
-- Node name is ':62' = 'counter0'
-- Equation name is 'counter0', location is LC023, type is buried.
counter0 = DFFE( _EQ001 $ !counter3, GLOBAL( cp), VCC, VCC, VCC);
_EQ001 = counter1 & counter2 & !counter3
# counter0 & !counter3;
-- Node name is ':61' = 'counter1'
-- Equation name is 'counter1', location is LC027, type is buried.
counter1 = DFFE( _EQ002 $ GND, GLOBAL( cp), VCC, VCC, VCC);
_EQ002 = !counter0 & counter1 & !counter2 & !counter3
# counter0 & !counter1 & !counter3;
-- Node name is ':60' = 'counter2'
-- Equation name is 'counter2', location is LC024, type is buried.
counter2 = DFFE( _EQ003 $ GND, GLOBAL( cp), VCC, VCC, VCC);
_EQ003 = counter0 & counter1 & !counter2 & !counter3
# !counter1 & counter2 & !counter3;
-- Node name is ':59' = 'counter3'
-- Equation name is 'counter3', location is LC025, type is buried.
counter3 = TFFE(!_EQ004, GLOBAL( cp), VCC, VCC, VCC);
_EQ004 = counter1 & counter2 & !counter3
# !counter3 & _X001;
_X001 = EXP( counter0 & counter1 & counter2);
-- Node name is ':69' = 'divi_cp'
-- Equation name is 'divi_cp', location is LC022, type is buried.
divi_cp = DFFE( _EQ005 $ GND, GLOBAL( cp), VCC, VCC, VCC);
_EQ005 = !counter0 & counter1 & counter2 & !counter3;
-- Node name is 'guarder_out' = ':126'
-- Equation name is 'guarder_out', type is output
guarder_out = DFFE( GND $ VCC, GLOBAL( cp), VCC, VCC, _EQ006);
_EQ006 = _X002 & _X003 & _X004 & _X005;
_X002 = EXP(!heat_in & _LC017 & q1 & !vol_in);
_X003 = EXP(!heat_in & !q0 & q1 & !vol_in);
_X004 = EXP(!heat_in & !q1 & !vol_in);
_X005 = EXP(!heat_in & !q0 & !vol_in);
-- Node name is ':77' = 'q0'
-- Equation name is 'q0', location is LC019, type is buried.
q0 = DFFE( curr_in $ GND, clk, VCC, VCC, VCC);
-- Node name is ':76' = 'q1'
-- Equation name is 'q1', location is LC020, type is buried.
q1 = DFFE( q0 $ GND, clk, VCC, VCC, VCC);
-- Node name is '|lpm_add_sub:130|addcore:adder|addcore:adder0|result_node2' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC017', type is buried
_LC017 = LCELL( q0 $ q0);
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Informationc:\software\project_beijing\cpld_v1.1\pwm_verilog hdl_v1.1\protect.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000S' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:01
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 5,358K
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