📄 pwm.rpt
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counter15;
-- Node name is '|lpm_add_sub:347|addcore:adder|addcore:adder0|result_node7' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC127', type is buried
_LC127 = LCELL( counter17 $ _EQ037);
_EQ037 = counter10 & counter11 & counter12 & counter13 & counter14 &
counter15 & counter16;
-- Node name is '|protect:U3|:71' = '|protect:U3|clk'
-- Equation name is '_LC090', type is buried
_LC090 = DFFE( _LC075 $ GND, GLOBAL( clock), VCC, VCC, VCC);
-- Node name is '|protect:U3|:62' = '|protect:U3|counter0'
-- Equation name is '_LC065', type is buried
_LC065 = DFFE( _EQ038 $ !_LC093, GLOBAL( clock), VCC, VCC, VCC);
_EQ038 = _LC074 & !_LC093 & _LC095
# _LC065 & !_LC093;
-- Node name is '|protect:U3|:61' = '|protect:U3|counter1'
-- Equation name is '_LC074', type is buried
_LC074 = DFFE( _EQ039 $ GND, GLOBAL( clock), VCC, VCC, VCC);
_EQ039 = !_LC065 & _LC074 & !_LC093 & !_LC095
# _LC065 & !_LC074 & !_LC093;
-- Node name is '|protect:U3|:60' = '|protect:U3|counter2'
-- Equation name is '_LC095', type is buried
_LC095 = DFFE( _EQ040 $ GND, GLOBAL( clock), VCC, VCC, VCC);
_EQ040 = _LC065 & _LC074 & !_LC093 & !_LC095
# !_LC074 & !_LC093 & _LC095;
-- Node name is '|protect:U3|:59' = '|protect:U3|counter3'
-- Equation name is '_LC093', type is buried
_LC093 = TFFE(!_EQ041, GLOBAL( clock), VCC, VCC, VCC);
_EQ041 = _LC074 & !_LC093 & _LC095
# !_LC093 & _X010;
_X010 = EXP( _LC065 & _LC074 & _LC095);
-- Node name is '|protect:U3|:69' = '|protect:U3|divi_cp'
-- Equation name is '_LC075', type is buried
_LC075 = DFFE( _EQ042 $ GND, GLOBAL( clock), VCC, VCC, VCC);
_EQ042 = !_LC065 & _LC074 & !_LC093 & _LC095;
-- Node name is '|protect:U3|lpm_add_sub:130|addcore:adder|addcore:adder0|result_node2' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC089', type is buried
_LC089 = LCELL( _LC094 $ _LC094);
-- Node name is '|protect:U3|:77' = '|protect:U3|q0'
-- Equation name is '_LC094', type is buried
_LC094 = DFFE( curr_in $ GND, _LC090, VCC, VCC, VCC);
-- Node name is '|protect:U3|:76' = '|protect:U3|q1'
-- Equation name is '_LC085', type is buried
_LC085 = DFFE( _LC094 $ GND, _LC090, VCC, VCC, VCC);
-- Node name is '|protect:U3|:126'
-- Equation name is '_LC081', type is buried
_LC081 = DFFE( GND $ VCC, GLOBAL( clock), VCC, VCC, _EQ043);
_EQ043 = _X011 & _X012 & _X013 & _X014;
_X011 = EXP(!heat_in & _LC085 & _LC089 & !vol_in);
_X012 = EXP(!heat_in & _LC085 & !_LC094 & !vol_in);
_X013 = EXP(!heat_in & !_LC085 & !vol_in);
_X014 = EXP(!heat_in & !_LC094 & !vol_in);
-- Node name is '~245~1'
-- Equation name is '~245~1', location is LC107, type is buried.
-- synthesized logic cell
_LC107 = LCELL( _EQ044 $ VCC);
_EQ044 = counter25 & _X015 & _X016
# !data_in5 & _X015 & _X016
# !counter27 & data_in7
# counter27 & !data_in7
# counter26 & !data_in6;
_X015 = EXP(!counter26 & data_in6);
_X016 = EXP( _LC082 & _LC109);
-- Node name is '~257~1'
-- Equation name is '~257~1', location is LC109, type is buried.
-- synthesized logic cell
_LC109 = LCELL(!counter25 $ data_in5);
-- Node name is '~258~1'
-- Equation name is '~258~1', location is LC082, type is buried.
-- synthesized logic cell
_LC082 = LCELL( _EQ045 $ GND);
_EQ045 = !counter20 & data_in0 & _X017 & _X018 & _X019 & _X020
# !counter21 & data_in1 & _X017 & _X018 & _X020
# !counter22 & data_in2 & _X017 & _X018
# !counter23 & data_in3 & _X017
# !counter24 & data_in4;
_X017 = EXP( counter24 & !data_in4);
_X018 = EXP( counter23 & !data_in3);
_X019 = EXP( counter21 & !data_in1);
_X020 = EXP( counter22 & !data_in2);
-- Node name is '~291~1'
-- Equation name is '~291~1', location is LC108, type is buried.
-- synthesized logic cell
_LC108 = LCELL( _EQ046 $ GND);
_EQ046 = !counter27 & !counter28 & data_in7 & flag & !_LC081
# !counter28 & flag & !_LC081 & _LC107
# !flag & !_LC081 & _LC108
# !counter27 & !counter28 & data_in7 & !_LC081 & _LC108
# !counter28 & !_LC081 & _LC107 & _LC108;
-- Node name is '~299~1'
-- Equation name is '~299~1', location is LC068, type is buried.
-- synthesized logic cell
_LC068 = LCELL( _EQ047 $ VCC);
_EQ047 = counter15 & _X021 & _X022
# !data_in5 & _X021 & _X022
# !counter17 & data_in7
# counter17 & !data_in7
# counter16 & !data_in6;
_X021 = EXP(!counter16 & data_in6);
_X022 = EXP( _LC067 & _LC086);
-- Node name is '~311~1'
-- Equation name is '~311~1', location is LC067, type is buried.
-- synthesized logic cell
_LC067 = LCELL(!counter15 $ data_in5);
-- Node name is '~312~1'
-- Equation name is '~312~1', location is LC086, type is buried.
-- synthesized logic cell
_LC086 = LCELL( _EQ048 $ GND);
_EQ048 = !counter10 & data_in0 & _X023 & _X024 & _X025 & _X026
# !counter11 & data_in1 & _X023 & _X024 & _X026
# !counter12 & data_in2 & _X023 & _X024
# !counter13 & data_in3 & _X023
# !counter14 & data_in4;
_X023 = EXP( counter14 & !data_in4);
_X024 = EXP( counter13 & !data_in3);
_X025 = EXP( counter11 & !data_in1);
_X026 = EXP( counter12 & !data_in2);
-- Node name is '~344~1'
-- Equation name is '~344~1', location is LC066, type is buried.
-- synthesized logic cell
_LC066 = LCELL( _EQ049 $ GND);
_EQ049 = !counter17 & !counter18 & data_in7 & !flag & !_LC081
# !counter18 & !flag & _LC068 & !_LC081
# flag & _LC066 & !_LC081
# !counter17 & !counter18 & data_in7 & _LC066 & !_LC081
# !counter18 & _LC066 & _LC068 & !_LC081;
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Informationc:\software\project_beijing\epm7064\cpld_v1.2\pwm_verilog hdl_v1.1\pwm.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000S' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:01
Database Builder 00:00:00
Logic Synthesizer 00:00:02
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:01
Assembler 00:00:02
-------------------------- --------
Total Time 00:00:06
Memory Allocated
-----------------
Peak memory allocated during compilation = 8,498K
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