📄 pwm.rpt
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Total I/O pins used: 17/80 ( 21%)
Total logic cells used: 57/128 ( 44%)
Total shareable expanders used: 26/128 ( 20%)
Total Turbo logic cells used: 57/128 ( 44%)
Total shareable expanders not available (n/a): 21/128 ( 16%)
Average fan-in: 7.45
Total fan-in: 425
Total input pins required: 12
Total fast input logic cells required: 0
Total output pins required: 2
Total bidirectional pins required: 0
Total reserved pins required 4
Total logic cells required: 57
Total flipflops required: 34
Total product terms required: 208
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 26
Synthesized logic cells: 8/ 128 ( 6%)
Device-Specific Information:c:\software\project_beijing\epm7064\cpld_v1.2\pwm_verilog hdl_v1.1\pwm.rpt
pwm
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
87 - - INPUT G 0 0 0 0 0 0 0 clock
96 (11) (A) INPUT 0 0 0 0 0 0 1 curr_in
1 (3) (A) INPUT 0 0 0 0 0 0 2 data_in0
2 (1) (A) INPUT 0 0 0 0 0 0 2 data_in1
5 (30) (B) INPUT 0 0 0 0 0 0 2 data_in2
6 (29) (B) INPUT 0 0 0 0 0 0 2 data_in3
7 (27) (B) INPUT 0 0 0 0 0 0 2 data_in4
8 (25) (B) INPUT 0 0 0 0 0 0 4 data_in5
9 (24) (B) INPUT 0 0 0 0 0 0 2 data_in6
10 (22) (B) INPUT 0 0 0 0 0 0 6 data_in7
97 (9) (A) INPUT 0 0 0 0 0 0 1 heat_in
98 (8) (A) INPUT 0 0 0 0 0 0 1 vol_in
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information:c:\software\project_beijing\epm7064\cpld_v1.2\pwm_verilog hdl_v1.1\pwm.rpt
pwm
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
16 46 C FF + t 0 0 0 0 2 0 0 pwm_A_out
17 45 C FF + t 0 0 0 0 2 0 0 pwm_B_out
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information:c:\software\project_beijing\epm7064\cpld_v1.2\pwm_verilog hdl_v1.1\pwm.rpt
pwm
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
(24) 35 C DFFE + t 0 0 0 0 1 1 0 |filter:U1|q1 (|filter:U1|:8)
- 103 G DFFE + t 0 0 0 1 6 1 1 |filter:U1|q0 (|filter:U1|:9)
- 34 C DFFE + t 0 0 0 0 1 1 0 |filter:U2|q1 (|filter:U2|:8)
- 79 E DFFE + t 0 0 0 1 6 1 1 |filter:U2|q0 (|filter:U2|:9)
(53) 83 F SOFT t 0 0 0 0 2 0 1 |lpm_add_sub:346|addcore:adder|addcore:adder0|result_node1
(72) 110 G SOFT t 0 0 0 0 3 0 1 |lpm_add_sub:346|addcore:adder|addcore:adder0|result_node2
(67) 102 G SOFT t 0 0 0 0 4 0 1 |lpm_add_sub:346|addcore:adder|addcore:adder0|result_node3
(73) 112 G SOFT t 0 0 0 0 5 0 1 |lpm_add_sub:346|addcore:adder|addcore:adder0|result_node4
- 111 G SOFT t 0 0 0 0 6 0 1 |lpm_add_sub:346|addcore:adder|addcore:adder0|result_node5
(83) 125 H SOFT t 0 0 0 0 7 0 1 |lpm_add_sub:346|addcore:adder|addcore:adder0|result_node6
(78) 118 H SOFT t 0 0 0 0 8 0 1 |lpm_add_sub:346|addcore:adder|addcore:adder0|result_node7
(85) 128 H SOFT t 0 0 0 0 9 0 1 |lpm_add_sub:346|addcore:adder|addcore:adder1|result_node0
(62) 96 F SOFT t 0 0 0 0 3 0 1 |lpm_add_sub:347|addcore:adder|addcore:adder0|result_node2
- 92 F SOFT t 0 0 0 0 4 0 1 |lpm_add_sub:347|addcore:adder|addcore:adder0|result_node3
(58) 91 F SOFT t 0 0 0 0 5 0 1 |lpm_add_sub:347|addcore:adder|addcore:adder0|result_node4
- 87 F SOFT t 0 0 0 0 6 0 1 |lpm_add_sub:347|addcore:adder|addcore:adder0|result_node5
(84) 126 H SOFT t 0 0 0 0 7 0 1 |lpm_add_sub:347|addcore:adder|addcore:adder0|result_node6
- 127 H SOFT t 0 0 0 0 8 0 1 |lpm_add_sub:347|addcore:adder|addcore:adder0|result_node7
(57) 89 F SOFT t 0 0 0 0 1 0 1 |protect:U3|lpm_add_sub:130|addcore:adder|addcore:adder0|result_node2
(60) 93 F TFFE + t 1 0 0 0 4 0 5 |protect:U3|counter3 (|protect:U3|:59)
- 95 F DFFE + t 0 0 0 0 4 0 5 |protect:U3|counter2 (|protect:U3|:60)
- 74 E DFFE + t 0 0 0 0 4 0 5 |protect:U3|counter1 (|protect:U3|:61)
(40) 65 E DFFE + t 0 0 0 0 4 0 5 |protect:U3|counter0 (|protect:U3|:62)
(47) 75 E DFFE + t 0 0 0 0 4 0 1 |protect:U3|divi_cp (|protect:U3|:69)
- 90 F DFFE + t 0 0 0 0 1 0 2 |protect:U3|clk (|protect:U3|:71)
(54) 85 F DFFE t 0 0 0 0 2 0 1 |protect:U3|q1 (|protect:U3|:76)
(61) 94 F DFFE t 0 0 0 1 1 0 3 |protect:U3|q0 (|protect:U3|:77)
(52) 81 F DFFE + t 4 0 0 2 3 0 4 |protect:U3|:126
- 106 G DFFE + t 2 1 1 0 11 0 13 counter28 (:94)
(69) 105 G DFFE + t 2 1 1 0 11 0 15 counter27 (:95)
(68) 104 G DFFE + t 2 1 1 0 11 0 14 counter26 (:96)
- 98 G DFFE + t 2 1 1 0 11 0 16 counter25 (:97)
- 100 G DFFE + t 2 1 1 0 11 0 16 counter24 (:98)
(64) 99 G DFFE + t 2 1 1 0 11 0 17 counter23 (:99)
(63) 97 G DFFE + t 2 1 1 0 11 0 18 counter22 (:100)
(65) 101 G DFFE + t 2 1 1 0 11 0 18 counter21 (:101)
(75) 113 H TFFE + t 0 0 0 0 9 0 19 counter20 (:102)
- 124 H TFFE + t 1 0 1 0 10 0 12 counter18 (:218)
- 122 H DFFE + t 2 2 0 0 11 0 14 counter17 (:219)
(79) 120 H DFFE + t 2 2 0 0 11 0 13 counter16 (:220)
(81) 123 H DFFE + t 2 1 1 0 11 0 15 counter15 (:221)
- 114 H DFFE + t 2 1 1 0 11 0 15 counter14 (:222)
(76) 115 H DFFE + t 2 1 1 0 11 0 16 counter13 (:223)
- 116 H DFFE + t 2 1 1 0 11 0 17 counter12 (:224)
(77) 117 H DFFE + t 2 0 1 0 10 0 16 counter11 (:225)
- 119 H DFFE + t 1 0 1 0 9 0 17 counter10 (:226)
(80) 121 H DFFE + t 6 2 0 0 19 0 23 flag (:233)
(70) 107 G SOFT s t 3 0 1 3 5 0 2 ~245~1
(71) 109 G SOFT s t 0 0 0 1 1 0 1 ~257~1
- 82 F SOFT s t 5 0 1 5 5 0 1 ~258~1
- 108 G LCELL s t 1 0 1 1 6 0 2 ~291~1
- 68 E SOFT s t 3 0 1 3 5 0 2 ~299~1
(41) 67 E SOFT s t 0 0 0 1 1 0 1 ~311~1
(55) 86 F SOFT s t 5 0 1 5 5 0 1 ~312~1
- 66 E LCELL s t 1 0 1 1 6 0 2 ~344~1
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information:c:\software\project_beijing\epm7064\cpld_v1.2\pwm_verilog hdl_v1.1\pwm.rpt
pwm
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'C':
Logic cells placed in LAB 'C'
+------- LC35 |filter:U1|q1
| +----- LC34 |filter:U2|q1
| | +--- LC46 pwm_A_out
| | | +- LC45 pwm_B_out
| | | |
| | | | Other LABs fed by signals
| | | | that feed LAB 'C'
LC | | | | | A B C D E F G H | Logic cells that feed LAB 'C':
LC35 -> - - * - | - - * - - - - - | <-- |filter:U1|q1
LC34 -> - - - * | - - * - - - - - | <-- |filter:U2|q1
Pin
87 -> - - - - | - - - - - - - - | <-- clock
LC103-> * - * - | - - * - - - - - | <-- |filter:U1|q0
LC79 -> - * - * | - - * - - - - - | <-- |filter:U2|q0
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information:c:\software\project_beijing\epm7064\cpld_v1.2\pwm_verilog hdl_v1.1\pwm.rpt
pwm
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'E':
Logic cells placed in LAB 'E'
+------------- LC79 |filter:U2|q0
| +----------- LC74 |protect:U3|counter1
| | +--------- LC65 |protect:U3|counter0
| | | +------- LC75 |protect:U3|divi_cp
| | | | +----- LC68 ~299~1
| | | | | +--- LC67 ~311~1
| | | | | | +- LC66 ~344~1
| | | | | | |
| | | | | | | Other LABs fed by signals
| | | | | | | that feed LAB 'E'
LC | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'E':
LC74 -> - * * * - - - | - - - - * * - - | <-- |protect:U3|counter1
LC65 -> - * * * - - - | - - - - * * - - | <-- |protect:U3|counter0
LC68 -> * - - - - - * | - - - - * - - - | <-- ~299~1
LC67 -> - - - - * - - | - - - - * - - - | <-- ~311~1
LC66 -> * - - - - - * | - - - - * - - - | <-- ~344~1
Pin
87 -> - - - - - - - | - - - - - - - - | <-- clock
8 -> - - - - * * - | - - - - * - * - | <-- data_in5
9 -> - - - - * - - | - - - - * - * - | <-- data_in6
10 -> * - - - * - * | - - - - * - * - | <-- data_in7
LC93 -> - * * * - - - | - - - - * * - - | <-- |protect:U3|counter3
LC95 -> - * * * - - - | - - - - * * - - | <-- |protect:U3|counter2
LC81 -> * - - - - - * | - - - - * - * - | <-- |protect:U3|:126
LC124-> * - - - - - * | - - - - * - - * | <-- counter18
LC122-> * - - - * - * | - - - - * - - * | <-- counter17
LC120-> - - - - * - - | - - - - * - - * | <-- counter16
LC123-> - - - - * * - | - - - - * * - * | <-- counter15
LC121-> * - - - - - * | - - - - * - * * | <-- flag
LC86 -> - - - - * - - | - - - - * - - - | <-- ~312~1
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information:c:\software\project_beijing\epm7064\cpld_v1.2\pwm_verilog hdl_v1.1\pwm.rpt
pwm
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'F':
Logic cells placed in LAB 'F'
+--------------------------- LC83 |lpm_add_sub:346|addcore:adder|addcore:adder0|result_node1
| +------------------------- LC96 |lpm_add_sub:347|addcore:adder|addcore:adder0|result_node2
| | +----------------------- LC92 |lpm_add_sub:347|addcore:adder|addcore:adder0|result_node3
| | | +--------------------- LC91 |lpm_add_sub:347|addcore:adder|addcore:adder0|result_node4
| | | | +------------------- LC87 |lpm_add_sub:347|addcore:adder|addcore:adder0|result_node5
| | | | | +----------------- LC89 |protect:U3|lpm_add_sub:130|addcore:adder|addcore:adder0|result_node2
| | | | | | +--------------- LC93 |protect:U3|counter3
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