📄 pwm.rpt
字号:
Project Informationc:\software\project_beijing\epm7064\cpld_v1.2\pwm_verilog hdl_v1.1\pwm.rpt
MAX+plus II Compiler Report File
Version 10.1 06/12/2001
Compiled: 03/17/2006 16:31:26
Copyright (C) 1988-2001 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
pwm EPM7128STC100-10 12 2 0 57 26 44 %
User Pins: 12 2 0
Project Informationc:\software\project_beijing\epm7064\cpld_v1.2\pwm_verilog hdl_v1.1\pwm.rpt
** AUTO GLOBAL SIGNALS **
INFO: Signal 'clock' chosen for auto global Clock
Project Informationc:\software\project_beijing\epm7064\cpld_v1.2\pwm_verilog hdl_v1.1\pwm.rpt
** PIN/LOCATION/CHIP ASSIGNMENTS **
Actual
User Assignments
Assignments (if different) Node Name
pwm@87 clock
pwm@96 curr_in
pwm@1 data_in0
pwm@2 data_in1
pwm@5 data_in2
pwm@6 data_in3
pwm@7 data_in4
pwm@8 data_in5
pwm@9 data_in6
pwm@10 data_in7
pwm@97 heat_in
pwm@16 pwm_A_out
pwm@17 pwm_B_out
pwm@98 vol_in
Project Informationc:\software\project_beijing\epm7064\cpld_v1.2\pwm_verilog hdl_v1.1\pwm.rpt
** FILE HIERARCHY **
|protect:U3|
|protect:U3|lpm_add_sub:128|
|protect:U3|lpm_add_sub:128|addcore:adder|
|protect:U3|lpm_add_sub:128|addcore:adder|addcore:adder0|
|protect:U3|lpm_add_sub:128|altshift:result_ext_latency_ffs|
|protect:U3|lpm_add_sub:128|altshift:carry_ext_latency_ffs|
|protect:U3|lpm_add_sub:128|altshift:oflow_ext_latency_ffs|
|protect:U3|lpm_add_sub:129|
|protect:U3|lpm_add_sub:129|addcore:adder|
|protect:U3|lpm_add_sub:129|addcore:adder|addcore:adder0|
|protect:U3|lpm_add_sub:129|altshift:result_ext_latency_ffs|
|protect:U3|lpm_add_sub:129|altshift:carry_ext_latency_ffs|
|protect:U3|lpm_add_sub:129|altshift:oflow_ext_latency_ffs|
|protect:U3|lpm_add_sub:130|
|protect:U3|lpm_add_sub:130|addcore:adder|
|protect:U3|lpm_add_sub:130|addcore:adder|addcore:adder0|
|protect:U3|lpm_add_sub:130|altshift:result_ext_latency_ffs|
|protect:U3|lpm_add_sub:130|altshift:carry_ext_latency_ffs|
|protect:U3|lpm_add_sub:130|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:346|
|lpm_add_sub:346|addcore:adder|
|lpm_add_sub:346|addcore:adder|addcore:adder1|
|lpm_add_sub:346|addcore:adder|addcore:adder0|
|lpm_add_sub:346|altshift:result_ext_latency_ffs|
|lpm_add_sub:346|altshift:carry_ext_latency_ffs|
|lpm_add_sub:346|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:347|
|lpm_add_sub:347|addcore:adder|
|lpm_add_sub:347|addcore:adder|addcore:adder1|
|lpm_add_sub:347|addcore:adder|addcore:adder0|
|lpm_add_sub:347|altshift:result_ext_latency_ffs|
|lpm_add_sub:347|altshift:carry_ext_latency_ffs|
|lpm_add_sub:347|altshift:oflow_ext_latency_ffs|
|filter:U1|
|filter:U1|lpm_add_sub:57|
|filter:U1|lpm_add_sub:57|addcore:adder|
|filter:U1|lpm_add_sub:57|addcore:adder|addcore:adder0|
|filter:U1|lpm_add_sub:57|altshift:result_ext_latency_ffs|
|filter:U1|lpm_add_sub:57|altshift:carry_ext_latency_ffs|
|filter:U1|lpm_add_sub:57|altshift:oflow_ext_latency_ffs|
|filter:U1|lpm_add_sub:58|
|filter:U1|lpm_add_sub:58|addcore:adder|
|filter:U1|lpm_add_sub:58|addcore:adder|addcore:adder0|
|filter:U1|lpm_add_sub:58|altshift:result_ext_latency_ffs|
|filter:U1|lpm_add_sub:58|altshift:carry_ext_latency_ffs|
|filter:U1|lpm_add_sub:58|altshift:oflow_ext_latency_ffs|
|filter:U2|
|filter:U2|lpm_add_sub:57|
|filter:U2|lpm_add_sub:57|addcore:adder|
|filter:U2|lpm_add_sub:57|addcore:adder|addcore:adder0|
|filter:U2|lpm_add_sub:57|altshift:result_ext_latency_ffs|
|filter:U2|lpm_add_sub:57|altshift:carry_ext_latency_ffs|
|filter:U2|lpm_add_sub:57|altshift:oflow_ext_latency_ffs|
|filter:U2|lpm_add_sub:58|
|filter:U2|lpm_add_sub:58|addcore:adder|
|filter:U2|lpm_add_sub:58|addcore:adder|addcore:adder0|
|filter:U2|lpm_add_sub:58|altshift:result_ext_latency_ffs|
|filter:U2|lpm_add_sub:58|altshift:carry_ext_latency_ffs|
|filter:U2|lpm_add_sub:58|altshift:oflow_ext_latency_ffs|
Device-Specific Information:c:\software\project_beijing\epm7064\cpld_v1.2\pwm_verilog hdl_v1.1\pwm.rpt
pwm
***** Logic for device 'pwm' compiled without errors.
Device: EPM7128STC100-10
Device Options:
Turbo Bit = ON
Security Bit = OFF
Enable JTAG Support = ON
User Code = ffff
MultiVolt I/O = OFF
R R R R R R R R R R R R R R
E E h c E E E E E E E E E E E E
S S v e u S S S V S S S S S S S S S
E E o a r E E E C c E E E V E E E E E E
R R l t r R R R C l R R R C R R R R R R
V V _ _ _ G V V V I G G G o G V V V C V V V V V V
E E i i i N E E E N N N N c N E E E I E E E E E E
D D n n n D D D D T D D D k D D D D O D D D D D D
----------------------------------------------------_
/ 100 98 96 94 92 90 88 86 84 82 80 78 76 |_
/ 99 97 95 93 91 89 87 85 83 81 79 77 |
data_in0 | 1 75 | RESERVED
data_in1 | 2 74 | GND
VCCIO | 3 73 | #TDO
#TDI | 4 72 | RESERVED
data_in2 | 5 71 | RESERVED
data_in3 | 6 70 | RESERVED
data_in4 | 7 69 | RESERVED
data_in5 | 8 68 | RESERVED
data_in6 | 9 67 | RESERVED
data_in7 | 10 66 | VCCIO
GND | 11 65 | RESERVED
RESERVED | 12 64 | RESERVED
RESERVED | 13 EPM7128STC100-10 63 | RESERVED
RESERVED | 14 62 | #TCK
#TMS | 15 61 | RESERVED
pwm_A_out | 16 60 | RESERVED
pwm_B_out | 17 59 | GND
VCCIO | 18 58 | RESERVED
RESERVED | 19 57 | RESERVED
RESERVED | 20 56 | RESERVED
RESERVED | 21 55 | RESERVED
RESERVED | 22 54 | RESERVED
RESERVED | 23 53 | RESERVED
RESERVED | 24 52 | RESERVED
RESERVED | 25 51 | VCCIO
| 27 29 31 33 35 37 39 41 43 45 47 49 _|
\ 26 28 30 32 34 36 38 40 42 44 46 48 50 |
\-----------------------------------------------------
G R R R R R R R V R R R G V R R R G R R R R R R R
N E E E E E E E C E E E N C E E E N E E E E E E E
D S S S S S S S C S S S D C S S S D S S S S S S S
E E E E E E E I E E E I E E E E E E E E E E
R R R R R R R O R R R N R R R R R R R R R R
V V V V V V V V V V T V V V V V V V V V V
E E E E E E E E E E E E E E E E E E E E
D D D D D D D D D D D D D D D D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information:c:\software\project_beijing\epm7064\cpld_v1.2\pwm_verilog hdl_v1.1\pwm.rpt
pwm
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 0/16( 0%) 5/10( 50%) 0/16( 0%) 0/36( 0%)
B: LC17 - LC32 0/16( 0%) 7/10( 70%) 0/16( 0%) 0/36( 0%)
C: LC33 - LC48 4/16( 25%) 3/10( 30%) 0/16( 0%) 4/36( 11%)
D: LC49 - LC64 0/16( 0%) 0/10( 0%) 0/16( 0%) 0/36( 0%)
E: LC65 - LC80 7/16( 43%) 0/10( 0%) 4/16( 25%) 17/36( 47%)
F: LC81 - LC96 14/16( 87%) 1/10( 10%) 15/16( 93%) 28/36( 77%)
G: LC97 - LC112 16/16(100%) 1/10( 10%) 13/16( 81%) 26/36( 72%)
H: LC113 - LC128 16/16(100%) 0/10( 0%) 15/16( 93%) 25/36( 69%)
Total dedicated input pins used: 1/4 ( 25%)
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -