fpurt_lib.vhd

ERC32 经典的sparc v7 cpu

-------------------------------------------------------------------------------
-- Modification history :
-------------------------------------------------------------------------------
-- Version No : | Author | Mod. Date : | Changes made :
-------------------------------------------------------------------------------
-- v 1.0        |        | 94-03-04    | first version
--.............................................................................
-------------------------------------------------------------------------------
-- Copyright MATRA MARCONI SPACE FRANCE
-------------------------------------------------------------------------------
---------|---------|---------|---------|---------|---------|---------|--------|

library IEEE;
use IEEE.Std_Logic_1164.all;
library MMS;
use MMS.StdSim.all;

package FPURTCompPck is

  component FPURTGeneric
    generic( -- Fake default timing values
      tCY      : time := 50 ns; -- Clock cycle
      tCHL     : time := 22 ns; -- CLock High and Low
      tAS      : time := 5 ns; -- A input setup
      tAH      : time := 1 ns; -- A input hold
      tDIS     : time := 5 ns; -- D input setup
      tDIH     : time := 1 ns; -- D input hold
      tDOD     : time := 7 ns; -- D output delay
      tDOH     : time := 6 ns; -- D data valid
      tDOFFL   : time := 7 ns; -- D output turn-off (FLUSH+)
      tDOHFL   : time := 6 ns; -- D output valid (FLUSH+)
      tDOFOE   : time := 7 ns; -- D output turn-off (DOE_N+)
      tDONOE   : time := 7 ns; -- D output turn-on (DOE_N-)
      tDOHOE   : time := 6 ns; -- D output valid (DOE_N-)
      tFIS     : time := 5 ns; -- FINS1/2 input setup
      tFIH     : time := 1 ns; -- FINS1/2 input hold
      tINS     : time := 5 ns; -- INST input setup
      tINH     : time := 1 ns; -- INST input hold
      tFXS     : time := 5 ns; -- FXACK input setup
      tFXH     : time := 1 ns; -- FXACK input hold
      tFLS     : time := 5 ns; -- FLUSH input setup
      tFLH     : time := 1 ns; -- FLUSH input hold
      tRES     : time := 5 ns; -- RESET_N input setup
      tREH     : time := 1 ns; -- RESET_N input hold
      tMHS     : time := 5 ns; -- MHOLD_N input setup
      tMHH     : time := 1 ns; -- MHOLD_N input hold
      tMDS     : time := 5 ns; -- MDS_N input setup
      tMDH     : time := 1 ns; -- MDS_N input hold
      tFHD     : time := 7 ns; -- FHOLD_N output delay
      tFHH     : time := 6 ns; -- FHOLD_N output valid
      tFHDFI   : time := 7 ns; -- FHOLD_N output delay (FINS1/2+)
      tFHDFL   : time := 7 ns; -- FHOLD_N output delay (FLUSH+)
      tFHDMH   : time := 7 ns; -- FHOLD_N output delay (MHOLD_N-)
      tFCCVD   : time := 7 ns; -- FCCV output delay
      tFCCVH   : time := 6 ns; -- FCCV output valid
      tFCCVDFL : time := 7 ns; -- FCCV output delay (FLUSH+)
      tFCCVDMH : time := 7 ns; -- FCCV output delay (MHOLD_N-)
      tFCCD    : time := 7 ns; -- FCC output delay
      tFCCH    : time := 6 ns; -- FCC output valid
      tFED     : time := 7 ns; -- FEXC_N output delay
      tFEH     : time := 6 ns; -- FEXC_N output valid
      tFND     : time := 7 ns; -- FNULL output delay
      tFNH     : time := 6 ns; -- FNULL output valid
      tAPS     : time := 7 ns; -- APAR input setup
      tAPH     : time := 6 ns; -- APAR input hold
      tDPIS    : time := 7 ns; -- DPAR input setup
      tDPIH    : time := 6 ns; -- DPAR input hold
      tDPOD    : time := 7 ns; -- DPAR output delay
      tDPOH    : time := 6 ns; -- DPAR output valid
      tIFS     : time := 7 ns; -- IFPAR input setup
      tIFH     : time := 6 ns; -- IFPAR input hold
      tFIPD    : time := 7 ns; -- FIPAR output delay
      tFIPH    : time := 6 ns; -- FIPAR output valid
      tMCD     : time := 7 ns; -- MCERR_N output delay
      tMCH     : time := 6 ns; -- MCERR_N output valid
      tCMS     : time := 5 ns; -- N602MODE_N, CMODE_N input setup
      tHAS     : time := 5 ns; -- HALT_N input setup
      tHAH     : time := 1 ns; -- HALT_N input hold
      tHAD     : time := 7 ns; -- HALT_N asserted to output disable delay
      tHAE     : time := 7 ns; -- HALT_N asserted to output enable delay
      tERD     : time := 7 ns; -- HWERROR_N output delay
      tERH     : time := 6 ns; -- HWERROR_N output valid
    
      tTCY     : time := 50 ns; -- TCLK Clock Cycle
      tTMS     : time := 5 ns; -- TMS setup
      tTMH     : time := 1 ns; -- TMS hold
      tTDIS    : time := 5 ns; -- TDI setup
      tTDIH    : time := 1 ns; -- TDI hold
      tTRS     : time := 5 ns; -- TRST_N setup
      tTRH     : time := 1 ns; -- TRST_N hold
      tTDOD    : time := 7 ns; -- TDO output delay
      tTDOH    : time := 6 ns  -- TDO output valid
    );
  
    port(
      Clk   : in std_logic; -- clock signal
    
      -- Integer Unit Interface Signals
      FP_N    : inout std_logic; --* Floating-point (Fp) Present
      FCC     : inout std_logic_vector(1 downto 0); --* Fp Condition Codes
      FCCV    : inout std_logic; --* Fp Condition Codes Valid
      FHOLD_N : inout std_logic; --* Fp Hold
      FEXC_N  : inout std_logic; --* Fp EXCeption
      FIPAR   : inout std_logic; --* Fpu to Iu control PARity
      FXACK   : in std_logic; -- Fp eXception ACKnowledge
      INST    : in std_logic; -- INSTruction fetch
      FINS1   : in std_logic; -- Fp INStruction in buffer 1
      FINS2   : in std_logic; -- Fp INStruction in buffer 2
      FLUSH   : in std_logic; -- Fp instruction fLUSH
      IFPAR   : in std_logic; -- Iu to Fpu control PARity
    
      -- System/Memory Interface Signals
      A          : in std_logic_vector(31 downto 0); -- Address bus
      APAR       : in std_logic; -- Address bus PARity
      D          : inout std_logic_vector(31 downto 0); -- Data bus
      DPAR       : inout std_logic; -- Data bus PARity
      DOE_N      : in std_logic;  -- Data Output Enable
      COE_N      : in std_logic;  -- Control Output Enable
      MHOLDA_N   : in std_logic;  -- Memory HOLD
      MHOLDB_N   : in std_logic;  -- Memory HOLD
      BHOLD_N    : in std_logic;  -- Bus HOLD
      MDS_N      : in std_logic;  -- Memory Data Strobe
      FNULL      : inout std_logic; --* Fpu NULLify cycle
      RESET_N    : in std_logic;  -- Reset signal
      HWERROR_N  : out std_logic; --Hardware error detected
      CMODE_N    : in std_logic;  -- master/Checker MODE
      MCERR_N    : out std_logic; -- Comparison Error
      N602MODE_N : in std_logic;  -- Normal 602MODE Operation
      HALT_N     : in std_logic;  -- Halt mode
    
      -- Coprocessor Interface Signals
      CHOLD_N  : in std_logic; -- Coprocessor hold.
      CCCV     : in std_logic; -- Coprocessor Condition Code Valid.

      -- Test Access Port (TAP) signals
      TCLK   : in std_logic;  -- Test CLocK
      TRST_N : in std_logic;  -- Test ReSeT
      TMS    : in std_logic;  -- Test Mode Select
      TDI    : in std_logic;  -- Test Data In
      TDO    : out std_logic  -- Test Data Out
    );
  end component; -- FPURTGeneric
  
  component FPURT
    generic(
          T : temperature := T_BOARD;
          V : voltage := V_BOARD;
          PROCES : proces_type := PROCES_BOARD;
          LOAD : capacitance := LOAD_BOARD
    );
  
    port(
      Clk   : in std_logic; -- clock signal
    
      -- Integer Unit Interface Signals
      FP_N    : inout std_logic; --* Floating-point (Fp) Present
      FCC     : inout std_logic_vector(1 downto 0); --* Fp Condition Codes
      FCCV    : inout std_logic; --* Fp Condition Codes Valid
      FHOLD_N : inout std_logic; --* Fp Hold
      FEXC_N  : inout std_logic; --* Fp EXCeption
      FIPAR   : inout std_logic; --* Fpu to Iu control PARity
      FXACK   : in std_logic; -- Fp eXception ACKnowledge
      INST    : in std_logic; -- INSTruction fetch
      FINS1   : in std_logic; -- Fp INStruction in buffer 1
      FINS2   : in std_logic; -- Fp INStruction in buffer 2
      FLUSH   : in std_logic; -- Fp instruction fLUSH
      IFPAR   : in std_logic; -- Iu to Fpu control PARity
    
      -- System/Memory Interface Signals
      A          : in std_logic_vector(31 downto 0); -- Address bus
      APAR       : in std_logic; -- Address bus PARity
      D          : inout std_logic_vector(31 downto 0); -- Data bus
      DPAR       : inout std_logic; -- Data bus PARity
      DOE_N      : in std_logic;  -- Data Output Enable
      COE_N      : in std_logic;  -- Control Output Enable
      MHOLDA_N   : in std_logic;  -- Memory HOLD
      MHOLDB_N   : in std_logic;  -- Memory HOLD
      BHOLD_N    : in std_logic;  -- Bus HOLD
      MDS_N      : in std_logic;  -- Memory Data Strobe
      FNULL      : inout std_logic; --* Fpu NULLify cycle
      RESET_N    : in std_logic;  -- Reset signal
      HWERROR_N  : out std_logic; -- Hardware error detected
      CMODE_N    : in std_logic;  -- master/Checker MODE
      MCERR_N    : out std_logic; -- Comparison Error
      N602MODE_N : in std_logic;  -- Normal 602MODE Operation
      HALT_N     : in std_logic;   -- Halt mode
    
      -- Coprocessor Interface Signals
      CHOLD_N  : in std_logic; -- Coprocessor hold.
      CCCV     : in std_logic; -- Coprocessor Condition Code Valid.

      -- Test Access Port (TAP) signals
      TCLK   : in std_logic;  -- Test CLocK
      TRST_N : in std_logic;  -- Test ReSeT
      TMS    : in std_logic;  -- Test Mode Select
      TDI    : in std_logic;  -- Test Data In
      TDO    : out std_logic  -- Test Data Out
    );
  end component; -- FPURT
  
end FPURTCompPck;
-------------------------------------------------------------------------------
-- File name : fpurt_pck.vhd
-- Title : FPURTPck
-- project : SPARC
-- Library : FPURTLIB
-- Author(s) : Maxime ROCCA, Jiri Gaisler
-- Purpose : 
--    Package containing SPARC FPURT specific VHDL constructs.
--
-- notes :   
--    To be included when anything defined in this file is used 
--    in another file.
-- 	
-------------------------------------------------------------------------------
-- Modification history :
-------------------------------------------------------------------------------
-- Version No : | Author | Mod. Date : | Changes made :
-------------------------------------------------------------------------------
-- v 1.0        |   MR   | 94-03-04    | first version
--.............................................................................
-- v 1.1        |   MR   | 94-05-03    | 2nd version
-- + VHDL bugs fixed.
--.............................................................................
-- v 1.2        |   JG   | 94-09-23    | 3nd version
-- Completely new implementation. Replaced MEIKO derived code with behavioral 
-- to allow free distribution. FPops with NaN as input do NOT behave as real 
-- device, but this shouldn't matter...
-------------------------------------------------------------------------------
-- Copyright MATRA MARCONI SPACE FRANCE
-- Copyright ESA/ESTEC
-------------------------------------------------------------------------------
---------|---------|---------|---------|---------|---------|---------|--------|

library IEEE;
use IEEE.Std_Logic_1164.all;
use ieee.Std_logic_arith.all;

library SPARC_LIB;
use SPARC_LIB.SparcPck.all;

use STD.TEXTIO.all;

package FPURTPck is

  -- Pseudo-functions that are constant tables:
  -- IsFPopRdDouble(Mnemonic) returns TRUE if Mnemonic is a FPop with rd double.
  -- IsFPopSourceRegDouble(Mnemonic) returns TRUE if Mnemonic is a FPop with 
  -- double precision source registers.
  -- IsFPopUnimp(Mnemonic) returns TRUE if Mnemonic is an unimplemented FPop.
  constant IsFPopRdDouble : MnemoTableType;
  constant IsFPopSourceRegDouble : MnemoTableType;
  constant IsFPopUnimp : MnemoTableType;
  
  -- Pseudo-function that emulates the ROM microcode for the computational core
  -- of the FPU. It returns a 64-bit data corresponding to the address (i.e the
  -- index in the table ranging between 0 and 255).
      
  -- Floating-point instruction type.
  type FPInstruction is record
    Mnemo          : SuperInstMnemonic; -- menmonic of a FP instruction.
    BitInstruction : std_logic_vector(31 downto 0); -- 32-bit value for the
                                                    -- instruction.
    BitAddress     : std_logic_vector(31 downto 0); -- 32-bit value for the
                                                    -- address.
    rs1 : natural; -- source register 1.
    rs2 : natural; -- source register 2.
    rd  : natural; -- destination register.
  end record; -- FPInstruction
  
  -- Modes of the FPU
  type FPUmodeType is (RESET_MODE, ERROR_MODE, 
                       EXECUTION, 
                       PENDING_EXCEPTION, EXCEPTION);

  -- Floating-point exception types
  type FPexcMnemonic is (
    FP_EXC_DETECTED,    -- FP exception has been detected
    IEEE_EXC,           -- IEEE 754 exception
    UNFINISHED_FPOP,    -- Unfinished FPop exception
    UNIMPLEMENTED_FPOP, -- Unimplemented FPop exception
    SEQUENCE_ERROR,     -- Sequence error exception
    DATA_BUS_ERROR,     -- Data bus error
    RESTARTABLE_ER      -- Restartable error
  );
  
  type FPexcVectorType is array(FPexcMnemonic) of boolean;
  
  
  --=================== FUNCTIONS declarations ====================
  
  ---------------------------------------------------------------------------
  -- Decode A as a SPARC instruction and returns the info under the form of
  -- a FPinstruction record.
  ---------------------------------------------------------------------------
  function FPtranscribe(A : std_logic_vector) return FPInstruction;
  
  ---------------------------------------------------------------------------
  -- Returns a non null value if a condition to generate the FHOLD_N signal is 
  -- encountered.
  ---------------------------------------------------------------------------
  function FHOLDcondition(signal FINS1 : std_logic;
                          signal FINS2 : std_logic;
                          signal ID1   : FPInstruction;
                          signal ID2   : FPInstruction;
                          signal E     : FPInstruction;
                          signal W     : FPInstruction;
                          W1           : FPInstruction;
                          signal FQ    : FPInstruction
                         ) return natural;
  
  ---------------------------------------------------------------------------
  -- Used in FHOLDcondition: dependency between FPop and FP load.
  ---------------------------------------------------------------------------
  function FPop_LDF(signal FPinst : FPInstruction;
                    RegD          : natural
                   ) return boolean;

  ---------------------------------------------------------------------------
  -- Used in FHOLDcondition: dependency between FPop and FP store.
  ---------------------------------------------------------------------------
  function FPop_STF(signal FPinst : FPInstruction;
                    RegD          : natural
                   ) return boolean;

  ---------------------------------------------------------------------------
  -- Used in FHOLDcondition: dependency between FP load and FPop.
  ---------------------------------------------------------------------------
  function LDF_FPop(signal W : FPInstruction;
                    ID       : FPInstruction
                   ) return boolean;

  ---------------------------------------------------------------------------
  -- Used in FHOLDcondition: dependency betwee FP load double and FPop.
  ---------------------------------------------------------------------------
  function LDDF_FPop(W1 : FPInstruction;
                     ID : FPInstruction
                    ) return boolean;



  ---------------------------------------------------------------------------
  -- Execution body for the FPURT: instructions are dispatched, executed, and
  -- the procedure returns the result together with the number of cycles it
  -- takes to get it. This procedure is the computational core of the FPU.
  ---------------------------------------------------------------------------
  procedure ExecuteFPop(FPbitInst   : std_logic_vector;
                        RS1vec      : std_logic_vector;
                        RS2vec      : std_logic_vector;
                        RD          : std_logic_vector;
                        TEM2        : std_logic;
                        DEBUG_FLAG  : boolean := FALSE; -- debugging purpose.
                        TestNb      : integer; -- debugging purpose.
                        Result      : out std_logic_vector;
                        tfcc        : out std_logic_vector;
                        texc        : out std_logic_vector;
                        FPexcVector : out FPexcVectorType;
                        NbCycles    : out integer;
                        Fdebug      : out text; -- debugging purpose.
                        FCtDebug    : out text  -- debugging purpose.
                       );