fpurt_lib.vhd

ERC32 经典的sparc v7 cpu

-------------------------------------------------------------------------------
-- File name : fpurt_gen_ent.vhd
-- Title : FPURTGeneric (entity)
-- project : SPARC
-- Library : FPURTLIB
-- Author(s) : Maxime ROCCA
-- Purpose : definition of entity FPURTGeneric
--
-- notes :   
-- 	
-------------------------------------------------------------------------------
-- Modification history :
-------------------------------------------------------------------------------
-- Version No : | Author | Mod. Date : | Changes made :
-------------------------------------------------------------------------------
-- v 1.0        |   MR   | 94-03-04    | first version
--.............................................................................
-- v 1.1        |   MR   | 94-05-27    | 2nd version
-- + modification of timing checkers.
------------------------------------------------------------------------------
-- Copyright MATRA MARCONI SPACE FRANCE
 
--  This library is free software; you can redistribute it and/or
--  modify it under the terms of the GNU Library General Public
--  License as published by the Free Software Foundation; either
--  version 2 of the License, or (at your option) any later version.
 
--  This library is distributed in the hope that it will be useful,
--  but WITHOUT ANY WARRANTY; without even the implied warranty of
--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
--  Library General Public License for more details.
 
--  You should have received a copy of the GNU Library General Public
--  License along with this library; if not, write to the Free
--  Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 
-------------------------------------------------------------------------------
---------|---------|---------|---------|---------|---------|---------|--------|

library IEEE;
use IEEE.Std_Logic_1164.all;
library MMS;
use MMS.StdIoImp.all;
use MMS.StdSim.all;
use MMS.StdTiming.all;

entity FPURTGeneric is
  generic( -- Fake default timing values
    tCY      : time := 50 ns; -- Clock cycle
    tCHL     : time := 22 ns; -- CLock High and Low
    tAS      : time := 5 ns; -- A input setup
    tAH      : time := 1 ns; -- A input hold
    tDIS     : time := 5 ns; -- D input setup
    tDIH     : time := 1 ns; -- D input hold
    tDOD     : time := 7 ns; -- D output delay
    tDOH     : time := 6 ns; -- D data valid
    tDOFFL   : time := 7 ns; -- D output turn-off (FLUSH+)
    tDOHFL   : time := 6 ns; -- D output valid (FLUSH+)
    tDOFOE   : time := 7 ns; -- D output turn-off (DOE_N+)
    tDONOE   : time := 7 ns; -- D output turn-on (DOE_N-)
    tDOHOE   : time := 6 ns; -- D output valid (DOE_N-)
    tFIS     : time := 5 ns; -- FINS1/2 input setup
    tFIH     : time := 1 ns; -- FINS1/2 input hold
    tINS     : time := 5 ns; -- INST input setup
    tINH     : time := 1 ns; -- INST input hold
    tFXS     : time := 5 ns; -- FXACK input setup
    tFXH     : time := 1 ns; -- FXACK input hold
    tFLS     : time := 5 ns; -- FLUSH input setup
    tFLH     : time := 1 ns; -- FLUSH input hold
    tRES     : time := 5 ns; -- RESET_N input setup
    tREH     : time := 1 ns; -- RESET_N input hold
    tMHS     : time := 5 ns; -- MHOLD_N input setup
    tMHH     : time := 1 ns; -- MHOLD_N input hold
    tMDS     : time := 5 ns; -- MDS_N input setup
    tMDH     : time := 1 ns; -- MDS_N input hold
    tFHD     : time := 7 ns; -- FHOLD_N output delay
    tFHH     : time := 6 ns; -- FHOLD_N output valid
    tFHDFI   : time := 7 ns; -- FHOLD_N output delay (FINS1/2+)
    tFHDFL   : time := 7 ns; -- FHOLD_N output delay (FLUSH+)
    tFHDMH   : time := 7 ns; -- FHOLD_N output delay (MHOLD_N-)
    tFCCVD   : time := 7 ns; -- FCCV output delay
    tFCCVH   : time := 6 ns; -- FCCV output valid
    tFCCVDFL : time := 7 ns; -- FCCV output delay (FLUSH+)
    tFCCVDMH : time := 7 ns; -- FCCV output delay (MHOLD_N-)
    tFCCD    : time := 7 ns; -- FCC output delay
    tFCCH    : time := 6 ns; -- FCC output valid
    tFED     : time := 7 ns; -- FEXC_N output delay
    tFEH     : time := 6 ns; -- FEXC_N output valid
    tFND     : time := 7 ns; -- FNULL output delay
    tFNH     : time := 6 ns; -- FNULL output valid
    tAPS     : time := 7 ns; -- APAR input setup
    tAPH     : time := 6 ns; -- APAR input hold
    tDPIS    : time := 7 ns; -- DPAR input setup
    tDPIH    : time := 6 ns; -- DPAR input hold
    tDPOD    : time := 7 ns; -- DPAR output delay
    tDPOH    : time := 6 ns; -- DPAR output valid
    tIFS     : time := 7 ns; -- IFPAR input setup
    tIFH     : time := 6 ns; -- IFPAR input hold
    tFIPD    : time := 7 ns; -- FIPAR output delay
    tFIPH    : time := 6 ns; -- FIPAR output valid
    tMCD     : time := 7 ns; -- MCERR_N output delay
    tMCH     : time := 6 ns; -- MCERR_N output valid
    tCMS     : time := 5 ns; -- N602MODE_N, CMODE_N input setup
    tHAS     : time := 5 ns; -- HALT_N input setup
    tHAH     : time := 1 ns; -- HALT_N input hold
    tHAD     : time := 7 ns; -- HALT_N asserted to output disable delay
    tHAE     : time := 7 ns; -- HALT_N asserted to output enable delay
    tERD     : time := 7 ns; -- HWERROR_N output delay
    tERH     : time := 6 ns; -- HWERROR_N output valid
    
    tTCY     : time := 50 ns; -- TCLK Clock Cycle
    tTMS     : time := 5 ns; -- TMS setup
    tTMH     : time := 1 ns; -- TMS hold
    tTDIS    : time := 5 ns; -- TDI setup
    tTDIH    : time := 1 ns; -- TDI hold
    tTRS     : time := 5 ns; -- TRST_N setup
    tTRH     : time := 1 ns; -- TRST_N hold
    tTDOD    : time := 7 ns; -- TDO output delay
    tTDOH    : time := 6 ns  -- TDO output valid
  );
  
  port(
    -- Note: signals which are functionally output signals but are actually
    -- inout signals because of the Master/Checker mode have an "*" in the 
    -- comments defining their function.

    CLK   : in std_logic; -- clock signal
    
    -- Integer Unit Interface Signals
    FP_N    : inout std_logic; -- Floating-point (Fp) Present
    FCC     : inout std_logic_vector(1 downto 0); --* Fp Condition Codes
    FCCV    : inout std_logic; --* Fp Condition Codes Valid
    FHOLD_N : inout std_logic; --* Fp Hold
    FEXC_N  : inout std_logic; --* Fp EXCeption
    FIPAR   : inout std_logic; --* Fpu to Iu control PARity
    FXACK   : in  std_logic; -- Fp eXception ACKnowledge
    INST    : in  std_logic; -- INSTruction fetch
    FINS1   : in  std_logic; -- Fp INStruction in buffer 1
    FINS2   : in  std_logic; -- Fp INStruction in buffer 2
    FLUSH   : in  std_logic; -- Fp instruction fLUSH
    IFPAR   : in  std_logic; -- Iu to Fpu control PARity
    
    -- System/Memory Interface Signals
    A          : in  std_logic_vector(31 downto 0); -- Address bus
    APAR       : in  std_logic; -- Address bus PARity
    D          : inout std_logic_vector(31 downto 0); -- Data bus
    DPAR       : inout std_logic; -- Data bus PARity
    DOE_N      : in  std_logic; -- Data Output Enable
    COE_N      : in  std_logic; -- Control Output Enable
    MHOLDA_N   : in  std_logic; -- Memory HOLD
    MHOLDB_N   : in  std_logic; -- Memory HOLD
    BHOLD_N    : in  std_logic; -- Bus HOLD
    MDS_N      : in  std_logic; -- Memory Data Strobe
    FNULL      : inout std_logic; --* Fpu NULLify cycle
    RESET_N    : in  std_logic; -- Reset signal
    HWERROR_N  : out std_logic; -- Hardware error detected
    CMODE_N    : in  std_logic; -- master/Checker MODE
    MCERR_N    : out std_logic; -- Comparison Error
    N602MODE_N : in  std_logic; -- Normal 602MODE Operation
    HALT_N     : in  std_logic; -- Halt mode
    
    -- Coprocessor Interface Signals
    CHOLD_N : in std_logic; -- Coprocessor hold.
    CCCV    : in std_logic; -- Coprocessor Condition Code Valid.

    -- Test Access Port (TAP) signals
    TCLK   : in  std_logic; -- Test CLocK
    TRST_N : in  std_logic; -- Test ReSeT
    TMS    : in  std_logic; -- Test Mode Select
    TDI    : in  std_logic; -- Test Data In
    TDO    : out std_logic  -- Test Data Out
  );
  
begin
  -- PUT HERE TIMING CHECKERS: SETUP & HOLD TIME + PULSE WIDTH CHECKERS.
  SigRESET_N    : SetupHoldCheck(RESET_N, CLK, EDGE => RISING,
                                 SETUP => tRES,  HOLD => tREH, 
                                 PATH => "RESET_N", 
                                 DelayedData => RESET_N'Delayed(abs(tREH)));
                                 
  SigN602MODE_N : SetupHoldCheck(N602MODE_N, CLK, EDGE => RISING,
                                 SETUP => tCMS,  HOLD => 0 ns, 
                                 PATH => "N602MODE_N", 
                                 DelayedData => N602MODE_N'Delayed(0 ns));
                                 
  SigCMODE_N    : SetupHoldCheck(CMODE_N, CLK, EDGE => RISING,
                                 SETUP => tCMS,  HOLD => 0 ns, 
                                 PATH => "CMODE_N", 
                                 DelayedData => CMODE_N'Delayed(0 ns));
                                 
  SigHALT_N     : SetupHoldCheck(HALT_N, CLK, EDGE => FALLING,
                                 SETUP => tHAS,  HOLD => tHAH, 
                                 PATH => "HALT_N", 
                                 DelayedData => HALT_N'Delayed(abs(tHAH)));
                                 
  SigTMS        : SetupHoldCheck(TMS, TCLK, EDGE => RISING,
                                 SETUP => tTMS,  HOLD => tTMH, 
                                 PATH => "TMS", 
                                 DelayedData => TMS'Delayed(abs(tTMH)));
                                 
  SigTDI        : SetupHoldCheck(TDI, TCLK, EDGE => RISING,
                                 SETUP => tTDIS,  HOLD => tTDIH, 
                                 PATH => "TDI", 
                                 DelayedData => TDI'Delayed(abs(tTDIH)));
                                 
  SigTRST_N     : SetupHoldCheck(TRST_N, TCLK, EDGE => RISING,
                                 SETUP => tTRS,  HOLD => tTRH, 
                                 PATH => "TRST_N", 
                                 DelayedData => TRST_N'Delayed(abs(tTRH)));
                                 
  
  CLKHigh : PulseCheck(CLK, LEVEL => '1', WIDTH => tCHL, 
                       SENSE => MINIMUM, PATH => "CLK");
                                
  CLKlow  : PulseCheck(CLK, LEVEL => '0', WIDTH => tCHL, 
                       SENSE => MINIMUM, PATH => "CLK");
    
  ---
  CLKCycle : process    -- Passive process: checks minimal value for CLK cycle.
    variable DeltaT   : time := 0 ns;
    variable LastEdge : time := -1 sec;
  begin
    if not(CHECK_ON) then
      wait; -- the process dies here....
    end if;
    
    wait on CLK until rising_edge(CLK);
    
    DeltaT   := now - LastEdge;
    LastEdge := now;
    
    assert (DeltaT >= tCY)
          report "Clock cycle violation: minimal value is " &
                 ToString(tCY) & "; value observed: " &
                 ToString(DeltaT) & "."
          severity warning;
    
  end process CLKCycle; 

  ----
  RESET_Nwidth : process    -- Passive process: checking on RESET_N width.
    constant MIN_NB_RESET_CYCLES : natural := 10;
    variable CountNbResetCycle : natural := 0;
  begin
    if not(CHECK_ON) then
      wait; -- the process dies here....
    end if;
    
    wait on CLK until rising_edge(CLK);
    
    if RESET_N = '1' then
      if CountNbResetCycle < MIN_NB_RESET_CYCLES and CountNbResetCycle /= 0 then
        assert FALSE
          report "Pulse width violation for RESET_N: should stay low for at " & 
                 "least " & ToString(MIN_NB_RESET_CYCLES) & 
                 " rising clock edges!"
          severity warning;
      end if;
      CountNbResetCycle := 0;
    elsif RESET_N = '0' then
      CountNbResetCycle := CountNbResetCycle + 1;
    end if;
    
  end process RESET_Nwidth; 
  
end FPURTGeneric;
-------------------------------------------------------------
-- File containing timing values for the FPURT VHDL model.
-- 
-- ALL THE TIMING PARAMETERS are given at 125 degrees C,  
-- 4.5 Volts and in worst case process conditions.
-- WARNING: minimal values for output signal propagation 
-- delay in data sheets are usually given in best conditions,  
-- i.e -55 Celsius, 5.5 Volts and best case process conditions.
-- They must be re-calculated for worst case conditions.
-------------------------------------------------------------

package FPURTTimPar is

  constant tCY      : time := 40 ns;
  constant tCHL     : time := 18 ns;
  constant tAS      : time :=  3 ns;
  constant tAH      : time :=  6 ns;
  constant tDIS     : time :=  3 ns;
  constant tDIH     : time :=  4 ns;
  constant tDOD     : time := 29 ns;
  constant tDOH     : time :=  9 ns;
  constant tDOFFL   : time := 31 ns;
  constant tDOHFL   : time :=  0 ns;
  constant tDOFOE   : time := 15 ns;
  constant tDONOE   : time := 15 ns;
  constant tDOHOE   : time :=  0 ns;
  constant tFIS     : time :=  9 ns;
  constant tFIH     : time :=  3 ns;
  constant tINS     : time := 16 ns; 
  constant tINH     : time :=  2 ns; 
  constant tFXS     : time := 16 ns; 
  constant tFXH     : time :=  2 ns; 
  constant tFLS     : time := 21 ns;
  constant tFLH     : time :=  2 ns;
  constant tRES     : time := 15 ns;
  constant tREH     : time :=  3 ns;
  constant tMHS     : time :=  7 ns;
  constant tMHH     : time :=  4 ns;
  constant tMDS     : time :=  5 ns;
  constant tMDH     : time :=  4 ns;
  constant tFHD     : time := 29 ns;
  constant tFHH     : time := 12 ns;
  constant tFHDFI   : time := 16 ns;
  constant tFHDFL   : time := 28 ns;
  constant tFHDMH   : time := 36 ns;
  constant tFCCVD   : time := 29 ns;
  constant tFCCVH   : time := 12 ns;
  constant tFCCVDFL : time := 28 ns; 
  constant tFCCVDMH : time := 36 ns;
  constant tFCCD    : time := 26 ns;
  constant tFCCH    : time := 12 ns;
  constant tFED     : time := 26 ns;
  constant tFEH     : time := 12 ns;
  constant tFND     : time := 20 ns;
  constant tFNH     : time :=  7 ns;
  constant tAPS     : time :=  3 ns;
  constant tAPH     : time :=  6 ns;
  constant tDPIS    : time :=  3 ns;
  constant tDPIH    : time :=  4 ns;
  constant tDPOD    : time := 29 ns;
  constant tDPOH    : time := 10 ns;
  constant tIFS     : time :=  9 ns;
  constant tIFH     : time :=  2 ns; 
  constant tFIPD    : time := 28 ns; 
  constant tFIPH    : time := 12 ns;
  constant tMCD     : time := 15 ns;
  constant tMCH     : time :=  7 ns;
  constant tCMS     : time := 10 ns;
  constant tHAS     : time :=  7 ns;
  constant tHAH     : time :=  4 ns;
  constant tHAD     : time := 15 ns; -- instead of 18
  constant tHAE     : time := 15 ns; -- instead of 18
  constant tERD     : time := 25 ns;
  constant tERH     : time :=  7 ns;
   
  constant tTCY     : time := 100 ns;  
  constant tTMS     : time := 20 ns;  
  constant tTMH     : time :=  8 ns;  
  constant tTDIS    : time := 20 ns;  
  constant tTDIH    : time :=  8 ns;  
  constant tTRS     : time := 20 ns;  
  constant tTRH     : time :=  8 ns;  
  constant tTDOD    : time := 30 ns;   
  constant tTDOH    : time := 12 ns; 

end FPURTTimPar;
-------------------------------------------------------------------------------
-- File name : fpurt_comp_pck.vhd
-- Title : FPURTCompPck
-- project : SPARC
-- Library : FPURTLIB
-- Author(s) : Maxime ROCCA
-- Purpose : package to declare components of entities for the FPURT.
-- 
-- notes : Use this package whenever a component is instanciated.
--