mms.vhd

ERC32 经典的sparc v7 cpu

	constant LOAD_BOARD : capacitance := 
		GetVal("stdsim.dft", "LOAD_BOARD") * pF;

	------------------------------------

	function SelectT (ENV : environment; SIM : sim_type) return temperature is
	begin
		case SIM is
			when SPECIFIC =>
				return GetVal("stdsim.dft", "T_BOARD_SPECIFIC") * Celsius;
			when MINIMUM =>
				case ENV is
					when COMMERCIAL => return 0 Celsius;
					when INDUSTRIAL => return -40 Celsius;
					when MILITARY => return -55 Celsius;
				end case;
			when TYPICAL => return 25 Celsius;
			when MAXIMUM =>
				case ENV is
					when COMMERCIAL => return 70 Celsius;
					when INDUSTRIAL => return 85 Celsius;
					when MILITARY => return 125 Celsius;
				end case;
		end case;
	end SelectT;	-- function

	function SelectV (SIM : sim_type) return voltage is
	begin
		case SIM is
			when SPECIFIC => return GetVal("stdsim.dft", "V_BOARD_SPECIFIC") * mV;
			when MINIMUM => return 5500 mV;
			when TYPICAL => return 5000 mV;
			when MAXIMUM => return 4500 mV;
		end case;
	end SelectV;	-- function

	function SelectProces (SIM : sim_type) return proces_type is
	begin
		case SIM is
			when SPECIFIC => 
				return proces_type'val(GetVal("stdsim.dft", "PROCES_BOARD_SPECIFIC",
				proces_type'pos(proces_type'low), proces_type'pos(proces_type'high)));
			when MINIMUM => return BEST;
			when TYPICAL => return TYPICAL;
			when MAXIMUM => return WORST;
		end case;
	end SelectProces;	-- function

	------------------------------------
	-- Calculation of board conditions
	------------------------------------

	constant T_BOARD : temperature := SelectT(ENVIRONMENT_BOARD, SIM_BOARD);
	constant V_BOARD : voltage := SelectV(SIM_BOARD);
	constant PROCES_BOARD : proces_type := SelectProces(SIM_BOARD);

end StdSim;	-- package body
------------------------------------------------------------
-- File name : stdtiming.vhd
-- Title : StdTiming
-- project : SPARC
-- Library : MMS
-- Author(s) : E. Laubacher
-- Purpose : package for standard timing declarations
-- notes : 
------------------------------------------------------------
-- Modification history :
------------------------------------------------------------
-- Version No : | Author | Mod. Date : | Changes made :
------------------------------------------------------------
-- v 1.0        | EL     | 92/06/14    | first version
--..........................................................
-- v 1.1        | MR     | 94/03/04    | 2nd version
-- + modification of function CalcDelay: new equation with
--   default capacitance of 50 pf, and timing parameters
--   in worst case conditions.
-- + 2 procedures for conditional setup/hold timing checking
--   added.
--..........................................................
-- v 1.2        | MR     | 94          |
-- + modification of function CalcDelay: equation with "ns"
--   instead of "ps".
------------------------------------------------------------
-- Copyright MATRA MARCONI SPACE FRANCE
------------------------------------------------------------

library IEEE;
use IEEE.Std_Logic_1164.all;
library MMS;
use MMS.StdSim.all;
use MMS.StdIoImp.all;
package StdTiming is

	----------------------------------
	-- Technology definitions
	----------------------------------

	type curve_parameter is array(natural range <>) of real;
	constant TECHNO_PREC : natural := 4;
	subtype slope_type is real;	-- pS/pF

	type technology is record
		TCurve : curve_parameter(0 to TECHNO_PREC - 1);
		VCurve : curve_parameter(0 to TECHNO_PREC - 1);
		KPMin : real;
		KPMax : real;
		LoadSlope : slope_type;	-- slope in ps/PF
	end record;	-- technology

	-- Note : KPTyp = 1.0

	----------------------------------
	-- usefull type for timing violation procedures
	----------------------------------

	type edge_type is (RISING, FALLING);
	type sense_type is (MINIMUM, MAXIMUM);

	----------------------------------
	-- Min and max functions on type time
	----------------------------------

	function MinTime(A, B : time) return time;
	function MaxTime(A, B : time) return time;

	-----------------------------------------------------------
	-- Function Name : CalcDelay
	-- Purpose : Reference delay calculation
	--
	-- Use :
	-- 	CalcDelay(BASE => TPLH,
	--						TECH => MHS_MC,
	--						T => 125 C,
	--						V => 5500 mV,
	--						PROCES => TYPICAL,
	--						LOAD => 50 pF);
	--
	-- Note : for setup, hold or pulse-width, the load has no meaning :
	--  just use the default value 50 pF
	--  The BASE value is given in the worst conditions: 125 Celcius,
	--  4.5 Volts and worst case process.
	-----------------------------------------------------------
	function CalcDelay(
		BASE : time;
		TECH : technology;
		T : temperature;
		V : voltage;
		PROCES : proces_type;
		LOAD : capacitance := 50 pF) return time;

	-----------------------------------------------------------
	-- Procedure Name : SetupHoldCheck
	-- Purpose : Check of setup-hold condition
	--  must be called concurrently (lasts Infinitely)
	-- 	Negative values accepted
	-- 	Verifies that the data does not change during the setup-hold interval
	-- 	The data is not allowed to change at the edge of the interval
	-- 	A 0-value for both edges produces no check
	--  The data is delayed at calling, since it is impossible in a procedure
	--  Beware that HOLD >= Tcycle leads to an incorrect behavior
	--
	-- Use (general form) :	
	-- 	SetupHoldCheck(	Data => Data,
	-- 				        	Ref => Clk,
	--   				     	 EDGE => FALLING,
	--          				SETUP => TSU, HOLD => THO,
	--           				PATH => "SEQUENCER/REG",
	--									DelayedData => Data'delayed(abs(HOLD)));
	--
	-----------------------------------------------------------
	procedure SetupHoldCheck (
		signal Data : std_ulogic;	-- as a subtype works for std_logic as well
		signal Ref : std_ulogic;
		constant EDGE : edge_type := RISING;
		constant SETUP, HOLD : time := 0 ns;
		constant PATH : string := "";
		signal DelayedData : std_ulogic);
			-- DelayedData must be set to Data'Delayed(abs(HOLD)) 
			--  for negative hold processing
	
	procedure SetupHoldCheck (
		signal Data : std_ulogic_vector;	
		signal Ref : std_ulogic;
		constant EDGE : edge_type := RISING;
		constant SETUP, HOLD : time := 0 ns;
		constant PATH : string := "";
		signal DelayedData : std_ulogic_vector);
			-- DelayedData must be set to Data'Delayed(abs(HOLD)) 
			--  for negative hold processing
	
	procedure SetupHoldCheck (
		signal Data : std_logic_vector;	-- not a subtype of std_ulogic_vector
		signal Ref : std_ulogic;
		constant EDGE : edge_type := RISING;
		constant SETUP, HOLD : time := 0 ns;
		constant PATH : string := "";
		signal DelayedData : std_logic_vector);
			-- DelayedData must be set to Data'Delayed(abs(HOLD)) 
			--  for negative hold processing
	
	-----------------------------------------------------------

  -----------------------------------------------------------------------------
  -- Conditional Setup/Hold timing checkers: the boolean signal EN_CHECKING  
  -- enables checking if it is TRUE. Similar to the procedure SetupHoldCheck.
  -----------------------------------------------------------------------------
  procedure CondSetupHoldCheck (signal Data   : std_ulogic;	
                                   -- as a subtype works for std_logic as well 
                                signal Ref    : std_ulogic;
                                constant EDGE : edge_type := RISING;
                                constant SETUP, HOLD : time := 0 ns;
                                constant PATH : string := "";
                                signal DelayedData : std_ulogic;
                                signal EN_CHECKING : boolean);

  procedure CondSetupHoldCheck (signal Data   : std_logic_vector;	
                                signal Ref    : std_ulogic;
                                constant EDGE : edge_type := RISING;
                                constant SETUP, HOLD : time := 0 ns;
                                constant PATH : string := "";
                                signal DelayedData : std_logic_vector;
                                signal EN_CHECKING : boolean);

	-----------------------------------------------------------
	-- Procedure Name : PulseCheck
	-- Purpose : Check of pulse width condition
	--  must be called concurrently (lasts Infinitely)
	-- 	Verifies that Pin stays longer than WIDTH in state LEVEL
	--  WIDTH is an acceptable value
	-- 	A 0-value produces no check
	--  No check before first event on Pin
	--
	-- Use :	PulseCheck (
	--					Pin => Clk,
	-- 					LEVEL => '1',
	--    			WIDTH => 15 ns,
	--          SENSE => MINIMUM,
	--    			PATH => "SEQUENCER/REG" );
	--
	-----------------------------------------------------------
	procedure PulseCheck (
		signal Pin : std_ulogic;
		constant LEVEL : std_ulogic;
		constant WIDTH : time := 0 ns;
		constant SENSE : sense_type := MINIMUM;
		constant PATH : string := "");
	
	-----------------------------------------------------------

	function TpDelay(	NewData : std_ulogic;
										TPLH, TPHL : time := 0 ns) return time;

	function TpDelay(	OldData, NewData : std_ulogic;
										TPLH, TPHL : time := 0 ns;
										TPZH, TPZL : time := 0 ns;
										TPHZ, TPLZ : time := 0 ns) return time;
										
	function TpDelay(	OldData, NewData : std_ulogic_vector;
										TPD : time := 0 ns;
										TPZD, TPDZ : time := 0 ns) return time;
										
	function TpDelay(	OldData, NewData : std_logic_vector;
										TPD : time := 0 ns;
										TPZD, TPDZ : time := 0 ns) return time;
										
end StdTiming;	-- package

-------------------------------------------------------------------------
-------------------------------------------------------------------------

Library IEEE;
use IEEE.Std_Logic_1164.all;
package body StdTiming is 

	-----------------------------------------------------------
	function MinTime (A, B : time) return time is
	begin
		if A <= B then return A;
		else return B;
		end if;
	end MinTime;	-- function

	-----------------------------------------------------------
	function MaxTime (A, B : time) return time is
	begin
		if A >= B then return A;
		else return B;
		end if;
	end MaxTime;	-- function

	-----------------------------------------------------------
	procedure SetupHoldCheck (
		signal Data : std_ulogic;
		signal Ref : std_ulogic;
		constant EDGE : edge_type := RISING;
		constant SETUP, HOLD : time := 0 ns;
		constant PATH : string := "";
		signal DelayedData : std_ulogic) is
			-- DelayedData must be set to Data'Delayed(abs(HOLD)) 
			--  for negative hold processing
		
		variable LastEdge : time;
		variable DeltaT : time;
		variable EdgeDetect : boolean;
	begin
		if (not CHECK_ON) or (SETUP = 0 ns and HOLD = 0 ns) then wait; end if;
		if SETUP + HOLD <= 0 ns then
			assert FALSE report "Impossible check on " & PATH &  
				". Setup : " & ToString(SETUP) & ". Hold : " & ToString(HOLD)
				severity warning;
			wait;
		end if;
		SkipInitProblems : loop
			wait on Ref until (EDGE = RISING and rising_edge(Ref)) or 
												(EDGE = FALLING and falling_edge(Ref));
				-- nothing before first edge of Ref
			LastEdge := now;
			if HOLD >= 0 ns then exit when Data'event or Data'last_event > 0 ns;
			else exit when DelayedData'event or DelayedData'last_event > 0 ns;
			end if;
		end loop SkipInitProblems;

		Infinite : loop
			EdgeDetect := (EDGE = RISING and rising_edge(Ref)) or 
										(EDGE = FALLING and falling_edge(Ref));
			--------------------
			if SETUP > 0 ns and HOLD >= 0 ns and EdgeDetect then
				DeltaT := Data'last_event;
				assert not(DeltaT <= SETUP) 
					report "Setup violation on " & PATH & " at time " & ToString(now) &
						". Observed : " & ToString(DeltaT) & ". Setup : " & ToString(SETUP)
					severity warning;
			end if;
			if HOLD > 0 ns and SETUP >= 0 ns and Data'event then
				DeltaT := now - LastEdge;
				assert not(DeltaT <= HOLD)
					report "Hold violation on " & PATH & " at time " & ToString(now) &
						". Observed : " & ToString(DeltaT) & ". Hold : " & ToString(HOLD)
					severity warning;
			end if;
			--------------------
			if SETUP < 0 ns and Data'event then
				DeltaT := now - LastEdge;
				assert not(-SETUP <= DeltaT and DeltaT <= HOLD)
					report "Timing violation on " & PATH & " at time " & ToString(now)
						& ". Observed : " & ToString(DeltaT) & 
						". Setup : " & ToString(SETUP) & ". Hold : " & ToString(HOLD)
					severity warning;
			end if;	-- nothing if no data event
			--------------------
			if HOLD < 0 ns and EdgeDetect then
				DeltaT := HOLD - DelayedData'last_event;
				assert not(-SETUP <= DeltaT and DeltaT <= HOLD)
					report "Timing violation on " & PATH & " at time " & ToString(now)
						& ". Observed : " & ToString(DeltaT) & 
						". Setup : " & ToString(SETUP) & ". Hold : " & ToString(HOLD)
					severity warning;
			end if;	-- nothing if no edge detected
			--------------------

			if EdgeDetect then LastEdge := now; end if;
			wait on Ref, Data;
		end loop Infinite;
	end SetupHoldCheck;	-- procedure
	
	--------------------------------------------

	procedure SetupHoldCheck (
		signal Data : std_ulogic_vector;	
		signal Ref : std_ulogic;
		constant EDGE : edge_type := RISING;
		constant SETUP, HOLD : time := 0 ns;
		constant PATH : string := "";
		signal DelayedData : std_ulogic_vector) is
			-- DelayedData must be set to Data'Delayed(abs(HOLD)) 
		
		variable LastEdge : time := 0 ns;
		variable DeltaT : time;