📄 sparc_lib.vhd
字号:
others => FALSE ); ------------------------------------- constant FPURs1IsIn : MnemoTableType := ( FADDs => TRUE, FADDd => TRUE, FADDq => TRUE, FSUBs => TRUE, FSUBd => TRUE, FSUBq => TRUE, FMULs => TRUE, FMULd => TRUE, FMULq => TRUE, FsMULd => TRUE, FdMULq => TRUE, -- SPARC v.8 only for FsMULd & FdMULq FDIVs => TRUE, FDIVd => TRUE, FDIVq => TRUE, FCMPs => TRUE, FCMPd => TRUE, FCMPq => TRUE, FCMPEs => TRUE, FCMPEd => TRUE, FCMPEq => TRUE, others => FALSE ); ------------------------------------- constant IsLoadInst : MnemoTableType := ( LD => TRUE, LDD => TRUE, LDSB => TRUE, LDUB => TRUE, LDSH => TRUE, LDUH => TRUE, LDA => TRUE, LDDA => TRUE, LDSBA => TRUE, LDUBA => TRUE, LDSHA => TRUE, LDUHA => TRUE, LDF => TRUE, LDDF => TRUE, LDFSR => TRUE, LDC => TRUE, LDDC => TRUE, LDCSR => TRUE, others => FALSE ); ------------------------------------- constant IsLoadDoubleInst : MnemoTableType := ( LDD => TRUE, LDDA => TRUE, LDDF => TRUE, LDDC => TRUE, others => FALSE ); ------------------------------------- constant IsLoadSingleInst : MnemoTableType := ( LD => TRUE, LDSB => TRUE, LDUB => TRUE, LDSH => TRUE, LDUH => TRUE, LDA => TRUE, LDSBA => TRUE, LDUBA => TRUE, LDSHA => TRUE, LDUHA => TRUE, LDF => TRUE, LDFSR => TRUE, LDC => TRUE, LDCSR => TRUE, others => FALSE ); ------------------------------------- constant IsLoadFP_CPInst : MnemoTableType := ( LDF => TRUE, LDDF => TRUE, LDFSR => TRUE, LDC => TRUE, LDDC => TRUE, LDCSR => TRUE, others => FALSE ); ------------------------------------- constant IsLoadByteInst : MnemoTableType := ( LDSB => TRUE, LDUB => TRUE, LDSBA => TRUE, LDUBA => TRUE, others => FALSE ); ------------------------------------- constant IsLoadHalfwordInst : MnemoTableType := ( LDSH => TRUE, LDUH => TRUE, LDSHA => TRUE, LDUHA => TRUE, others => FALSE ); ------------------------------------- constant IsLoadInstASI : MnemoTableType := ( LDA => TRUE, LDDA => TRUE, LDSBA => TRUE, LDUBA => TRUE, LDSHA => TRUE, LDUHA => TRUE, others => FALSE ); ------------------------------------- constant IsStoreInst : MnemoTableType := ( ST => TRUE, I_STD => TRUE, STH => TRUE, STB => TRUE, STA => TRUE, STDA => TRUE, STHA => TRUE, STBA => TRUE, STF => TRUE, STDF => TRUE, STFSR => TRUE, STDFQ => TRUE, STC => TRUE, STDC => TRUE, STCSR => TRUE, STDCQ => TRUE, others => FALSE ); ------------------------------------- constant IsStoreFP_CPInst : MnemoTableType := ( STF => TRUE, STDF => TRUE, STFSR => TRUE, STDFQ => TRUE, STC => TRUE, STDC => TRUE, STCSR => TRUE, STDCQ => TRUE, others => FALSE ); ------------------------------------- constant IsStoreDoubleInst : MnemoTableType := ( I_STD => TRUE, STDA => TRUE, STDF => TRUE, STDFQ => TRUE, STDC => TRUE, STDCQ => TRUE, others => FALSE ); ------------------------------------- constant IsStoreInstASI : MnemoTableType := ( STA => TRUE, STDA => TRUE, STBA => TRUE, STHA => TRUE, others => FALSE ); ------------------------------------- constant IsStoreSingleInst : MnemoTableType := ( ST => TRUE, STH => TRUE, STB => TRUE, STA => TRUE, STBA => TRUE, STHA => TRUE, STF => TRUE, STFSR => TRUE, STC => TRUE, STCSR => TRUE, others => FALSE ); ------------------------------------- constant IsFPinst : MnemoTableType := ( LDDF => TRUE, LDF => TRUE, LDFSR => TRUE, STDF => TRUE, STF => TRUE, STFSR => TRUE, STDFQ => TRUE, FBN => TRUE, FBNE => TRUE, FBLG => TRUE, FBUL => TRUE, FBL => TRUE, FBUG => TRUE, FBG => TRUE, FBU => TRUE, FBA => TRUE, FBE => TRUE, FBUE => TRUE, FBGE => TRUE, FBUGE => TRUE, FBLE => TRUE, FBULE => TRUE, FBO => TRUE, FiTOs => TRUE, FiTOd => TRUE, FiTOq => TRUE, FsTOi => TRUE, FdTOi => TRUE, FqTOi => TRUE, FsTOd => TRUE, FsTOq => TRUE, FdTOs => TRUE, FdTOq => TRUE, FqTOs => TRUE, FqTOd => TRUE, FMOVs => TRUE, FNEGs => TRUE, FABSs => TRUE, FSQRTs => TRUE, FSQRTd => TRUE, FSQRTq => TRUE, FADDs => TRUE, FADDd => TRUE, FADDq => TRUE, FSUBs => TRUE, FSUBd => TRUE, FSUBq => TRUE, FMULs => TRUE, FMULd => TRUE, FMULq => TRUE, FsMULd => TRUE, FdMULq => TRUE, -- SPARC v.8 only for FsMULd & FdMULq FDIVs => TRUE, FDIVd => TRUE, FDIVq => TRUE, FCMPs => TRUE, FCMPd => TRUE, FCMPq => TRUE, FCMPEs => TRUE, FCMPEd => TRUE, FCMPEq => TRUE, others => FALSE ); ------------------------------------- constant IsFPop : MnemoTableType := ( FiTOs => TRUE, FiTOd => TRUE, FiTOq => TRUE, FsTOi => TRUE, FdTOi => TRUE, FqTOi => TRUE, FsTOd => TRUE, FsTOq => TRUE, FdTOs => TRUE, FdTOq => TRUE, FqTOs => TRUE, FqTOd => TRUE, FMOVs => TRUE, FNEGs => TRUE, FABSs => TRUE, FSQRTs => TRUE, FSQRTd => TRUE, FSQRTq => TRUE, FADDs => TRUE, FADDd => TRUE, FADDq => TRUE, FSUBs => TRUE, FSUBd => TRUE, FSUBq => TRUE, FMULs => TRUE, FMULd => TRUE, FMULq => TRUE, FsMULd => TRUE, FdMULq => TRUE, -- SPARC v.8 only for FsMULd & FdMULq FDIVs => TRUE, FDIVd => TRUE, FDIVq => TRUE, FCMPs => TRUE, FCMPd => TRUE, FCMPq => TRUE, FCMPEs => TRUE, FCMPEd => TRUE, FCMPEq => TRUE, others => FALSE ); ------------------------------------- constant IsFPopDouble : MnemoTableType := ( FdTOi => TRUE, FdTOs => TRUE, FdTOq => TRUE, FSQRTd => TRUE, FADDd => TRUE, FSUBd => TRUE, FMULd => TRUE, FdMULq => TRUE, -- SPARC v.8 only for FsMULd & FdMULq FDIVd => TRUE, FCMPd => TRUE, FCMPEd => TRUE, others => FALSE ); ------------------------------------- constant IsFPopQuad : MnemoTableType := ( FqTOi => TRUE, FqTOs => TRUE, FqTOd => TRUE, FSQRTq => TRUE, FADDq => TRUE, FSUBq => TRUE, FMULq => TRUE, FDIVq => TRUE, FCMPq => TRUE, FCMPEq => TRUE, others => FALSE ); ------------------------------------- constant IsFCMP : MnemoTableType := ( FCMPs => TRUE, FCMPd => TRUE, FCMPq => TRUE, FCMPEs => TRUE, FCMPEd => TRUE, FCMPEq => TRUE, others => FALSE ); ------------------------------------- function GetIndex(n : natural; CWP : std_logic_vector) return natural is variable Temp, CWPvar : natural; begin assert (n >= 0 and n < 32) report "(GetIndex): wrong value for n!" severity error; if (n >= 0 and n <= 7) then return n; -- global registers. end if; CWPvar := ToNatural(CWP); assert CWPvar < NWINDOWS report "(GetIndex): wrong value for CWP!" severity error; Temp := (n - 8 + CWPvar*16) mod (16*NWINDOWS) + 8; return Temp; end GetIndex; -- function ------------------------------------- function Transcribe(A : std_logic_vector) return Instruction is constant L : natural := A'length; alias op : std_logic_vector(1 downto 0) is A(31 downto 30); alias op2 : std_logic_vector(2 downto 0) is A(24 downto 22); alias op3 : std_logic_vector(5 downto 0) is A(24 downto 19); alias opf : std_logic_vector(8 downto 0) is A(13 downto 5); alias cond : std_logic_vector(3 downto 0) is A(28 downto 25); alias asi : std_logic_vector(7 downto 0) is A(12 downto 5); alias i : std_logic is A(13); alias a_bit : std_logic is A(29); alias rd : std_logic_vector(4 downto 0) is A(29 downto 25); alias rs1 : std_logic_vector(4 downto 0) is A(18 downto 14); alias rs2 : std_logic_vector(4 downto 0) is A( 4 downto 0); alias simm13 : std_logic_vector(12 downto 0) is A(12 downto 0); alias disp30 : std_logic_vector(29 downto 0) is A(29 downto 0); alias disp22 : std_logic_vector(21 downto 0) is A(21 downto 0); variable Result : Instruction; begin assert L = 32 report "(Transcribe): invalid vector length!" severity error; if VecUnknown(A) then Result.Mnemo := XXX; return Result; -- exit function here if unknown bits in A end if; -- For almost all instructions, these 5 fields are relevant: so -- they are assigned for all instructions. Result.BitInstr := A; Result.rd := ToNatural(rd); Result.rs1 := ToNatural(rs1); Result.rs2 := ToNatural(rs2); Result.simm13 := ToNatural(simm13); if i = '0' then Result.i := 0; -- Result.i is a natural. else Result.i := 1; end if; case op is -- 1st level when "00" => ---------- OP testing --------------- Result.disp22 := ToNatural(disp22); -- Common statement for op="00". Result.Annul := FALSE; -- explicit assignment to FALSE. case op2 is -- 2nd level when "100" => -------------- OP + OP2 testing -------------- Result.Mnemo := SETHI; when "010" => -------------- OP + OP2 testing -------------- case cond is -- 3rd level when "0000" => Result.Mnemo := BN; when "0001" => Result.Mnemo := BE; when "0010" => Result.Mnemo := BLE; when "0011" => Result.Mnemo := BL; when "0100" => Result.Mnemo := BLEU; when "0101" => Result.Mnemo := BCS; when "0110" => Result.Mnemo := BNEG; when "0111" => Result.Mnemo := BVS; when "1000" => Result.Mnemo := BA; when "1001" => Result.Mnemo := BNE; when "1010" => Result.Mnemo := BG; when "1011" => Result.Mnemo := BGE; when "1100" => Result.Mnemo := BGU; when "1101" => Result.Mnemo := BCC; when "1110" => Result.Mnemo := BPOS; when "1111" => Result.Mnemo := BVC; when others => NULL; end case; -- cond if a_bit = '0' then Result.a := 0; -- Result.a is a natural. else Result.a := 1; end if; when "110" => -------------- OP + OP2 testing -------------- case cond is -- 3rd level when "0000" => Result.Mnemo := FBN; when "0001" => Result.Mnemo := FBNE; when "0010" => Result.Mnemo := FBLG; when "0011" => Result.Mnemo := FBUL; when "0100" => Result.Mnemo := FBL; when "0101" => Result.Mnemo := FBUG; when "0110" => Result.Mnemo := FBG; when "0111" => Result.Mnemo := FBU; when "1000" => Result.Mnemo := FBA; when "1001" => Result.Mnemo := FBE; when "1010" => Result.Mnemo := FBUE; when "1011" => Result.Mnemo := FBGE; when "1100" => Result.Mnemo := FBUGE; when "1101" => Result.Mnemo := FBLE;
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -