sparc_lib.vhd

ERC32 经典的sparc v7 cpu

--                              WIM        : out std_logic_vector;--gd 
                              Y          : inout std_logic_vector; 
--                              Y          : out std_logic_vector;--gd 
                              TrapVector : inout TrapVectorType);
                              
  -----------------------------------------------------------------------------
  -- This procedure detects trap conditions for LDSTUBA and SWAPA instructions.
  -- Address calculation is not performed for sequencing reasons.
  -----------------------------------------------------------------------------
  procedure LoadStoreSwapInstruction(EX         : Instruction;
                                     S          : std_logic;
                                     CWP        : std_logic_vector;
                                     RegFile    : RegisterFile;
                                     TrapVector : inout TrapVectorType);
                                 
  -----------------------------------------------------------------------------
  -- Execution of trap instructions. Computation of the trap number when
  -- the trap is taken and assignment of the tt field of the TBR with the com-
  -- -puted value.
  -----------------------------------------------------------------------------
  procedure TiccInstruction(EX         : Instruction;
                            CWP        : std_logic_vector;
                            icc        : std_logic_vector;
                            RegFile    : RegisterFile;
                            tt         : out std_logic_vector;
                            TrapVector : inout TrapVectorType);
                            
  -----------------------------------------------------------------------------
  -- This procedure executes OPcc (operations affecting the Integer Condition
  -- Codes) "in advance" ("anticipated" execution).
  -- Results are stored in temporary data objects ResultOPcc, YTemp and 
  -- iccTemp.
  -- These temp. data objects are used to assign the register file and icc of
  -- the PSR (ex.: for OPcc = ADDcc, execution is performed in the procedure
  -- ExecuteOPcc. The register file and icc are assigned in the procedure
  -- AddSubInstruction).
  -----------------------------------------------------------------------------
  procedure ExecuteOPcc(ID         : Instruction;
                        RegFile    : RegisterFile;
                        CWP        : std_logic_vector;
                        icc        : std_logic_vector;
                        Y          : std_logic_vector;
                        ResultOPcc : out std_logic_vector;
                        iccTemp    : out std_logic_vector;
                        YTemp      : out std_logic_vector);
                        
  -----------------------------------------------------------------------------
  -- "Anticipated" execution of Bicc, to calculate the branching address in 
  -- time. No action is taken in the execution body procedure for these instr.
  ----------------------------------------------------------------------------
  procedure ExecuteBicc(iccTemp     : std_logic_vector;
                        icc         : std_logic_vector;
                        nID         : inout Instruction;
                        CurrentAddr : inout std_logic_vector;
                        TakenBr     : out boolean);
                        
  -----------------------------------------------------------------------------
  -- Same as above for Floating-point branch.
  -----------------------------------------------------------------------------
  procedure ExecuteFBfcc(signal fcc  : std_logic_vector;
                         nID         : inout Instruction;
                         CurrentAddr : inout std_logic_vector;
                         TakenBr     : out boolean);
                        
  -----------------------------------------------------------------------------
  -- Puts nID in the instruction buffer (FIFO)
  -----------------------------------------------------------------------------
  procedure PutInBufferQueue(nID         : Instruction;
                             Buf1IsValid : inout boolean;
                             InstBuffer1 : inout Instruction;
                             Buf2IsValid : inout boolean;
                             InstBuffer2 : inout Instruction);
                             
  -----------------------------------------------------------------------------
  -- Sets flag IOPcase to TRUE if an IOP is to be scheduled.
  -----------------------------------------------------------------------------
  procedure IOPscheduling(InstBuffer1 : Instruction;
                          nID         : Instruction;
                          signal ID   : Instruction;
                          signal EX   : Instruction;
                          signal WR   : Instruction;
                          IOPcase     : out boolean);

  -----------------------------------------------------------------------------
  -- Gets an instruction from the instruction buffer (FIFO) and puts it 
  -- in nIDTemp.
  -----------------------------------------------------------------------------
  procedure GetFromBufferQueue(Buf1IsValid : inout boolean;
                               InstBuffer1 : inout Instruction;
                               Buf2IsValid : inout boolean;
                               InstBuffer2 : inout Instruction;
                               nIDTemp     : out Instruction);
                              
  -----------------------------------------------------------------------------
  -- Fetch data on data bus when WR is load instruction and the register rd of
  -- instruction WR is not 0.
  -----------------------------------------------------------------------------
  procedure DataFetchForLoadAndLdstInst(
                          CurrentAddr     : std_logic_vector;
                          signal D        : std_logic_vector;
                          CWP             : std_logic_vector;
                          signal WR       : Instruction;
                          WR1             : Instruction;
                          RegFile         : inout RegisterFile;
                          SwapData        : out std_logic_vector);

  -----------------------------------------------------------------------------
  -- This procedure fetches the data that appears on the bus when a cache miss
  -- case is encountered and serviced. It is essentially used for load and 
  -- load-store instructions.
  -----------------------------------------------------------------------------
  procedure DataFetchWhenCacheMiss(Addr     : std_logic_vector;
                                   signal D : std_logic_vector;
                                   CWP      : std_logic_vector;
                                   WR1      : Instruction;
                                   WR2      : Instruction;
                                   RegFile  : inout RegisterFile);

  -----------------------------------------------------------------------------
  -- Procedure to perform setup and hold time violation checking for the 
  -- data bus and its parity bit.
  -----------------------------------------------------------------------------
  procedure DbusSetupHoldCheck (signal Data    : std_logic_vector;  
                                signal CLK     : std_ulogic;
                                signal XHOLD_N : std_ulogic;
                                constant SETUP, HOLD : time := 0 ns;
                                constant PATH  : string := "";
                                signal DelayedData : std_logic_vector;
                                signal EN_CHECKING : boolean);

  procedure DbusSetupHoldCheck (signal Data    : std_ulogic;  
                                signal CLK     : std_ulogic;
                                signal XHOLD_N : std_ulogic;
                                constant SETUP, HOLD : time := 0 ns;
                                constant PATH  : string := "";
                                signal DelayedData : std_ulogic;
                                signal EN_CHECKING : boolean);

end SparcPck; -- package


-------------------------------------------------------------------------------
-------------------------------------------------------------------------------

package body SparcPck is
  
  -------------------------------------
  constant IsOPcc : IsOPccType :=(
       ADDcc    => TRUE,
       ANDcc    => TRUE,
       ORcc     => TRUE,
       XORcc    => TRUE,
       SUBcc    => TRUE,
       ANDNcc   => TRUE,
       ORNcc    => TRUE,
       XNORcc   => TRUE,
       ADDXcc   => TRUE,
       UMULcc   => TRUE, -- SPARC v.8
       SMULcc   => TRUE, -- SPARC v.8
       SUBXcc   => TRUE,
       UDIVcc   => TRUE, -- SPARC v.8
       SDIVcc   => TRUE, -- SPARC v.8
       TADDcc   => TRUE,
       TSUBcc   => TRUE,
       TADDccTV => TRUE,
       TSUBccTV => TRUE,
       MULScc   => TRUE,
       others => FALSE
  );
  
  -------------------------------------
  constant IsBicc : IsBranchingInstType :=(
       BN   => TRUE,
       BE   => TRUE,
       BLE  => TRUE,
       BL   => TRUE,
       BLEU => TRUE,
       BCS  => TRUE,
       BNEG => TRUE,
       BVS  => TRUE,
       BA   => TRUE,
       BNE  => TRUE,
       BG   => TRUE,
       BGE  => TRUE,
       BGU  => TRUE,
       BCC  => TRUE,
       BPOS => TRUE,
       BVC  => TRUE,
       others => FALSE
  );
  
  -------------------------------------
  constant IsFBfcc : IsBranchingInstType :=(
       FBN   => TRUE,
       FBNE  => TRUE,
       FBLG  => TRUE,
       FBUL  => TRUE,
       FBL   => TRUE,
       FBUG  => TRUE,
       FBG   => TRUE,
       FBU   => TRUE,
       FBA   => TRUE,
       FBE   => TRUE,
       FBUE  => TRUE,
       FBGE  => TRUE,
       FBUGE => TRUE,
       FBLE  => TRUE,
       FBULE => TRUE,
       FBO   => TRUE,
       others => FALSE
  );
  -------------------------------------
  constant IsCBccc : IsBranchingInstType :=(
       CBN   => TRUE,
       CB123 => TRUE,
       CB12  => TRUE,
       CB13  => TRUE,
       CB1   => TRUE,
       CB23  => TRUE,
       CB2   => TRUE,
       CB3   => TRUE,
       CBA   => TRUE,
       CB0   => TRUE,
       CB03  => TRUE,
       CB02  => TRUE,
       CB023 => TRUE,
       CB01  => TRUE,
       CB013 => TRUE,
       CB012 => TRUE,
       others => FALSE
  );
  
  -------------------------------------
  constant IURs1Rs2AreIn : MnemoTableType := (
     LD      => TRUE, LDA   => TRUE, LDC   => TRUE, LDCSR => TRUE,
     LDD     => TRUE,
     LDDA    => TRUE, LDDC  => TRUE, LDDF  => TRUE, LDF   => TRUE,
     LDFSR   => TRUE,
     LDSB    => TRUE, LDSBA => TRUE, LDSH  => TRUE, LDSHA => TRUE,
     LDSTUB  => TRUE,
     LDSTUBA => TRUE, LDUB  => TRUE, LDUBA => TRUE, LDUH  => TRUE,
     LDUHA   => TRUE,
     ST      => TRUE, STA   => TRUE, STB   => TRUE, STBA  => TRUE,
     STC     => TRUE,
     STCSR   => TRUE, I_STD   => TRUE, STDA  => TRUE, STDC  => TRUE,
     STDCQ   => TRUE,
     STDF    => TRUE, STDFQ => TRUE, STF   => TRUE, STFSR => TRUE,
     STH     => TRUE,
     STHA    => TRUE, SWAP  => TRUE, SWAPA => TRUE,
        --- Arithmetic/Logical/Shift Instruction Mnemonics ---
     ADD    => TRUE, ADDcc    => TRUE, ADDX   => TRUE, ADDXcc   => TRUE,
     I_AND  => TRUE,
     ANDcc  => TRUE, ANDN     => TRUE, ANDNcc => TRUE, MULScc   => TRUE,
     I_OR   => TRUE,
     ORcc   => TRUE, ORN      => TRUE, ORNcc  => TRUE, SLL      => TRUE,
     SRA    => TRUE,
     SRL    => TRUE, SUB      => TRUE, SUBcc  => TRUE, SUBX     => TRUE,
     SUBXcc => TRUE,
     TADDcc => TRUE, TADDccTV => TRUE, TSUBcc => TRUE, TSUBccTV => TRUE,
     XNOR   => TRUE,
     XNORcc => TRUE, I_XOR    => TRUE, XORcc  => TRUE,
        --- Control Transfer Instruction Mnemonics ---
     JMPL => TRUE, RESTORE => TRUE, RETT => TRUE, SAVE => TRUE,
     TN   => TRUE, TE      => TRUE,
     TLE  => TRUE, TL      => TRUE, TLEU => TRUE, TCS  => TRUE, TNEG => TRUE,
     TVS  => TRUE, TA      => TRUE, TNE  => TRUE, TG   => TRUE, TGE  => TRUE,
     TGU  => TRUE, TCC     => TRUE, TPOS => TRUE, TVC  => TRUE,
        --- Write Control Register Instruction Mnemonics ---
     WRPSR => TRUE, WRTBR => TRUE, WRWIM => TRUE, WRY => TRUE,
        --- Miscellaneous Instruction Mnemonics ---
     FLUSH => TRUE, -- IFLUSH instead of FLUSH in SPARC v.7
     RDASR => TRUE, WRASR => TRUE, -- SPARC v.8 only
        --- Integer Multiply/Divide Instructions Mnemonics ---
                   --- SPARC Version 8 only ---
     UMUL   => TRUE, UMULcc => TRUE, SMUL   => TRUE, SMULcc => TRUE,
     UDIV   => TRUE,
     UDIVcc => TRUE, SDIV   => TRUE, SDIVcc => TRUE,