sparc_lib.vhd

ERC32 经典的sparc v7 cpu

  );
  
  type TrapModeType is (
     NOTRAP,       -- no trap condition
     SYNCH_TRAP,   -- SYNCHronous trap
     ASYNCH_TRAP   -- ASYNCHronous trap
  );
  

--============== FUNCTIONS DECLARATIONS  ======================================

  
  -----------------------------------------------------------------------------
  -- GetIndex emulates the windowing scheme of the windowed register file by
  -- returning the right index for this register file.
  -- n: the input index (0<n<31)
  -- CWP: Current Window Pointer
  -----------------------------------------------------------------------------
  function GetIndex(n : natural; CWP : std_logic_vector) return natural;
  
  -----------------------------------------------------------------------------
  -- This function "decodes" a 32-bit vector considered as being a SPARC
  -- instruction by returning a record "Instruction" containing all the  
  -- meaningful information needed to execute this instruction.
  -- A must be a 32-bit vector. The function will crash if A'length is less
  -- than 32, and assert an error if greater than 32. Moreover, A should be
  -- defined as A(31:0), i.e MSB with highest index.
  -- Note: SPARC v.8 instructions RDASR, WRASR & STBAR are not decoded by this
  -- function.
  -----------------------------------------------------------------------------
  function Transcribe(A : std_logic_vector) return Instruction;
  
  -----------------------------------------------------------------------------
  -- Evaluates the icc and returns TRUE if the branch should be taken.
  -----------------------------------------------------------------------------
  function iccEvaluation(Mnemonic : SuperInstMnemonic;
                         icc      : std_logic_vector) return boolean;
                         
  -----------------------------------------------------------------------------
  -- Same as iccEvaluation for Ticc instructions.
  -----------------------------------------------------------------------------
  function TiccEval(Mnemonic : SuperInstMnemonic;
                    icc      : std_logic_vector) return boolean;
                         
  -----------------------------------------------------------------------------
  -- Same as above for FPU with fcc.
  -----------------------------------------------------------------------------
  function fccEvaluation(Mnemonic   : SuperInstMnemonic;
                         signal fcc : std_logic_vector) return boolean;

  -----------------------------------------------------------------------------
  -- Returns TRUE if there is a register dependency between rd and InstB 
  -- (i.e one of the source register of InstB is the destination register rd).
  -- Valid for register of the IU (not the FP registers).
  -----------------------------------------------------------------------------
  function IURegDependency(rd    : natural;
                           InstB : Instruction) return boolean;
                           
  -----------------------------------------------------------------------------
  -- Returns TRUE if there is a register dependency between rd and InstB 
  -- (i.e one of the source register of InstB is the destination register rd).
  -- Valid for registers of the FPU (FP registers).
  -- WARNING: THIS FUNCTION IS OBSOLETE and kept here for information.
  -----------------------------------------------------------------------------
--  function FPURegDependency(rd    : natural;
--                            Mnemo : SuperInstMnemonic;
--                            rs1   : natural;
--                            rs2   : natural) return boolean;

  -----------------------------------------------------------------------------
  -- Computes the value of the address for a load, store or load-store 
  -- instruction.
  -----------------------------------------------------------------------------
  function LoadORStoreORSwapAddrCalc(Inst    : Instruction;
                                     CWP     : std_logic_vector;
                                     RegFile : RegisterFile) 
                                        return std_logic_vector;

  -----------------------------------------------------------------------------
  -- Computes the odd parity over a given std_logic_vector
  -----------------------------------------------------------------------------
  function OddParityOf(Vec : std_logic_vector) return std_logic;

--============== PROCEDURES DECLARATIONS ======================================

  -----------------------------------------------------------------------------
  -- This procedure detects traps (for asynchronous traps) and does the opera-
  -- -tions to be performed when a trap case is present.
  -- All std_logic_vector parameters must be 32 bits long.
  -- Interrupting traps (asynchronous traps) are also taken care of.
  -----------------------------------------------------------------------------
  procedure TrapHandler(signal EX   : Instruction;
                        signal WR   : Instruction;
                               WR1  : Instruction;
                               WR2  : Instruction;
                        pIRLvar     : natural;
                        IRLvar      : natural;
                        TBR         : inout std_logic_vector;
                        PSR         : inout std_logic_vector;
                        TrapVector  : inout TrapVectorType;
                        Mode        : inout ModeType;
                        TrapMode    : out TrapModeType;
                        pPrevAddr   : inout std_logic_vector;
                        PrevAddr    : inout std_logic_vector;
                        CurrentAddr : inout std_logic_vector;
 --                       RegFile     : out RegisterFile); --gd 2208
 -- we dont want to erase the old value
                        RegFile     : inout RegisterFile);
  
  -----------------------------------------------------------------------------
  -- This procedure does the dispatching for instruction execution. Trap flags 
  -- are set when traps are detected for each "family" of instructions.
  -- ResultOpcc, iccTemp, YTemp are parameters for "anticipated" execution of
  -- certain instructions (OPcc instructions).
  -- ResultOpcc, Y, YTemp, PSR, TBR, WIM lengths must be 32 bits long.
  -- iccTemp length must be 4 bits long.
  -----------------------------------------------------------------------------
  procedure ExecutionBody(signal FP_N : std_logic;
                          signal IFT_N: std_logic;
                          signal EX   : Instruction;
                          ResultOpcc  : std_logic_vector;
                          YTemp       : std_logic_vector;
                          iccTemp     : inout std_logic_vector;
                          Y           : inout std_logic_vector;
                          PSR         : inout std_logic_vector;
                          TBR         : inout std_logic_vector;
                          WIM         : inout std_logic_vector;
                          RegFile     : inout RegisterFile;
                          Mode        : inout ModeType;
                          TrapVector  : inout TrapVectorType);
  
  -----------------------------------------------------------------------------
  -- Execution of LOAD instructions. The procedure only detects trap conditions.
  -- The address of the data to load is computed earlier so that the data can
  -- be fetched in time on the bus.
  -----------------------------------------------------------------------------
  procedure LoadInstruction(signal FP_N : std_logic;
                            EX          : Instruction;
                            PSR         : std_logic_vector;
                            RegFile     : RegisterFile;
                            TrapVector  : inout TrapVectorType);
                            
  -----------------------------------------------------------------------------
  -- Execute the store instructions. Detects trap conditions and set the trap
  -- vector accordingly.
  -----------------------------------------------------------------------------
  procedure StoreInstruction(signal FP_N : std_logic;
                             EX          : Instruction;
                             PSR         : std_logic_vector;
                             RegFile     : RegisterFile;
                             TrapVector  : inout TrapVectorType);
                             
  -----------------------------------------------------------------------------
  -- This procedure performs all the logical operations. OPcc being executed by
  -- "anticipation", their results are used (with the parameters ResultOPcc and
  -- iccTemp) to assign the register file and icc of the PSR.
  -----------------------------------------------------------------------------
  procedure LogicalInstruction(EX         : Instruction;
                               CWP        : std_logic_vector;
                               ResultOPcc : std_logic_vector;
                               iccTemp    : std_logic_vector;
                               RegFile    : inout RegisterFile;
                               icc        : out std_logic_vector);
                               
  -----------------------------------------------------------------------------
  -- Additions and substractions are performed here. Same as above for OPcc and
  -- parameters.
  -----------------------------------------------------------------------------
  procedure AddSubInstruction(EX         : Instruction;
                              CWP        : std_logic_vector;
                              ResultOPcc : std_logic_vector;
                              iccTemp    : std_logic_vector;
                              RegFile    : inout RegisterFile;
                              icc        : inout std_logic_vector);
  
                            
  -----------------------------------------------------------------------------
  -- Logical and arithmetic shifts. Integer conditions codes are not affected 
  -- by these instructions.
  -----------------------------------------------------------------------------
  procedure ShiftInstruction(EX         : Instruction;
                             CWP        : std_logic_vector;
                             RegFile    : inout RegisterFile);
                             
  -----------------------------------------------------------------------------
  -- Same as AddSubInstruction but with tags. There can be trap conditions.
  -----------------------------------------------------------------------------
  procedure TaggedAddSubbInst(EX         : Instruction;
                              CWP        : std_logic_vector;
                              ResultOPcc : std_logic_vector;
                              iccTemp    : std_logic_vector;
                              icc        : out std_logic_vector;
                              RegFile    : inout RegisterFile;
--                              RegFile    : out RegisterFile; --gd 2208
                              TrapVector : inout TrapVectorType);
                              
  -----------------------------------------------------------------------------
  -- This is an OPcc instruction (affecting the Integer Condition Codes); so it
  -- is executed by anticipation in ExecuteOPcc. Y, icc and RegFile are assigned
  -- with their right value YTemp, iccTemp, ResultOPcc computed in ExecuteOPcc.
  -----------------------------------------------------------------------------
  procedure MultiplyStepInst(EX         : Instruction;
                             CWP        : std_logic_vector;
                             ResultOPcc : std_logic_vector;
                             iccTemp    : std_logic_vector;
                             YTemp      : std_logic_vector;
                             Y          : out std_logic_vector;
                             icc        : out std_logic_vector;
                             RegFile    : inout RegisterFile); --gd 2208
--                             RegFile    : out RegisterFile);
  
  -----------------------------------------------------------------------------
  -- Execution of SAVE/RESTORE instructions. 
  -- Note that the destination register of these instructions is in the NEW
  -- window whereas the source registers come from the OLD window.
  -----------------------------------------------------------------------------
  procedure SaveRestoreInst(EX         : Instruction;
                            WIM        : std_logic_vector;
                            CWP        : inout std_logic_vector;
                            RegFile    : inout RegisterFile;
                            TrapVector : inout TrapVectorType);
                            
  -----------------------------------------------------------------------------
  -- Execution of the instr. RETT, leaving aside the branching address calcula-
  -- -tion which is performed by "anticipation" in ID stage.
  -----------------------------------------------------------------------------
  procedure RettInstruction(EX         : Instruction;
                            RegFile    : RegisterFile;
                            WIM        : std_logic_vector;
                            PSR        : inout std_logic_vector;
                            Mode       : inout ModeType;
                            tt         : out std_logic_vector;
                            TrapVector : inout TrapVectorType);
                            
  -----------------------------------------------------------------------------
  -- Execution of the instr. JMPL, leaving aside the branching address calcula-
  -- -tion which is performed by "anticipation" in ID stage.
  -----------------------------------------------------------------------------
  procedure JmplInstruction(EX         : Instruction;
                            CWP        : std_logic_vector;
                            RegFile    : inout RegisterFile;
                            TrapVector : inout TrapVectorType);
                            
  -----------------------------------------------------------------------------
  -- Branching address calculation for JMPL/RETT instructions.
  -- Done by "anticipation" in ID stage.
  -----------------------------------------------------------------------------
  procedure JmplRettAddrCalc(ID          : Instruction;
                             CWP         : std_logic_vector;
                             RegFile     : RegisterFile;
                             CurrentAddr : out std_logic_vector);
                            
  -----------------------------------------------------------------------------
  -- Instructions reading the state registers are executed in this procedure.
  -- If some trap conditions are encountered, the trap vector is assigned with 
  -- the correct values to tell the trap handler what to do.
  -----------------------------------------------------------------------------
  procedure ReadStateRegInst(EX         : Instruction;
                             PSR        : std_logic_vector;
                             TBR        : std_logic_vector;
                             WIM        : std_logic_vector;
                             Y          : std_logic_vector;
                             TrapVector : inout TrapVectorType;
                             RegFile    : inout RegisterFile);
 --                            RegFile    : out RegisterFile);
                             
  -----------------------------------------------------------------------------
  -- Instructions writing the state registers are executed in this procedure.
  -- Same as above for trap detection.
  -----------------------------------------------------------------------------
  procedure WriteStateRegInst(EX         : Instruction;
                              RegFile    : RegisterFile;
                              PSR        : inout std_logic_vector; 
                              iccTemp    : out std_logic_vector;
                              TBR        : inout std_logic_vector; 
--                              TBR        : out std_logic_vector;--gd 
                              WIM        : inout std_logic_vector;