sparc_lib.vhd

ERC32 经典的sparc v7 cpu

-------------------------------------------------------------------------------
-- File name : sparc_pck.vhd
-- Title : SparcPck
-- project : SPARC 
-- Library : SPARC_LIB
-- Author(s) : Maxime ROCCA, Jiri Gaisler
-- Purpose : package containing definitions for SPARC environment
-- notes : 
-- 	
-------------------------------------------------------------------------------
-- Modification history :
-------------------------------------------------------------------------------
-- Version No : | Author | Mod. Date : | Changes made :
-------------------------------------------------------------------------------
-- v 1.0        |  MR    | 94-03-04    | first version
--.............................................................................
-- v 1.1        |  MR    | 94-05-03    | 2nd version
-- + OddParityOf function has been modified (output inverted).
-- + procedure IOPscheduling: erroneous specification in issue 4 of the IURT
--   device specification about hardware interlocks for JMPL, CALL and LOAD 
--   double.
-- + modif. hardware trap priority.
--.............................................................................
-- v 1.2        |  MR    | 94-05-27    | 3rd version
-- + define specific timing checker for D & DPAR signals
--.............................................................................
-- v 1.3        |  RC    | 95-12-11    | 4rd version
-- + define RegFile and TrapVector as an inout 
--.............................................................................
-- v 1.4        |  JG    | 96-03-06    | 5rd version
-- + bug fix: correct stored PC and nPC after tapped LD and LDD
-------------------------------------------------------------------------------
-- Copyright MATRA MARCONI SPACE FRANCE
-- Copyright ESA/ESTEC

--  This library is free software; you can redistribute it and/or
--  modify it under the terms of the GNU Library General Public
--  License as published by the Free Software Foundation; either
--  version 2 of the License, or (at your option) any later version.
 
--  This library is distributed in the hope that it will be useful,
--  but WITHOUT ANY WARRANTY; without even the implied warranty of
--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
--  Library General Public License for more details.
 
--  You should have received a copy of the GNU Library General Public
--  License along with this library; if not, write to the Free
--  Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 
-------------------------------------------------------------------------------
---------|---------|---------|---------|---------|---------|---------|--------|

library IEEE;
use IEEE.Std_Logic_1164.all;
library MMS;
use MMS.StdRtl.all;
use MMS.StdSim.all;
use MMS.StdIoImp.all;


package SparcPck is


  -- Size of data bus transfer.
  constant BYTE       : natural := 0;
  constant HALFWORD   : natural := 1;
  constant WORDTYPE   : natural := 2;
  constant DOUBLEWORD : natural := 3;

  -- Address Space Identifiers.
  constant USER_INST       : natural :=  8;
  constant USER_DATA       : natural := 10;
  constant SUPERVISOR_INST : natural :=  9;
  constant SUPERVISOR_DATA : natural := 11;

  -- Number of implemented windows
  constant NWINDOWS : natural := 8;
  
  -- Bit numbers for icc  
  constant N_ICC : natural := 3;
  constant Z_ICC : natural := 2;
  constant V_ICC : natural := 1;
  constant C_ICC : natural := 0;
  
  -- Values for the impl & ver fields of the PSR
  constant PSR_IMPL : std_logic_vector(3 downto 0) := "0001";
  constant PSR_VER  : std_logic_vector(3 downto 0) := "0001";
  constant TBR3_DOWNTO_0  : std_logic_vector(3 downto 0) := "0000";
            
  -- Processor states or modes.
  type ModeType is (RESET_MODE, ERROR_MODE, EXECUTE_MODE);

  -- Mnemonics for instructions.
  type SuperInstMnemonic is (  -- including pseudo-instructions
     -- pseudo-instruction mnemonics for modelling purposes
     XXX, ILLEGAL, IOP, NOTHING, ANNULLED,
     
     -- SPARC instruction set
        --- Load/Store Instruction Mnemonics ---
     LD      , LDA     , LDC      , LDCSR   , LDD     ,
     LDDA    , LDDC    , LDDF     , LDF     , LDFSR   ,
     LDSB    , LDSBA   , LDSH     , LDSHA   , LDSTUB  ,
     LDSTUBA , LDUB    , LDUBA    , LDUH    , LDUHA   ,
     ST      , STA     , STB      , STBA    , STC     ,
     STCSR   , I_STD     , STDA     , STDC    , STDCQ   ,
     STDF    , STDFQ   , STF      , STFSR   , STH     ,
     STHA    , SWAP    , SWAPA    ,
        --- Arithmetic/Logical/Shift Instruction Mnemonics ---
     ADD     , ADDcc   , ADDX     , ADDXcc  , I_AND   ,
     ANDcc   , ANDN    , ANDNcc   , MULScc  , I_OR    ,
     ORcc    , ORN     , ORNcc    , SLL     , SRA     ,
     SRL     , SUB     , SUBcc    , SUBX    , SUBXcc  ,
     TADDcc  , TADDccTV, TSUBcc   , TSUBccTV, XNOR    ,
     XNORcc  , I_XOR   , XORcc    ,
        --- Control Transfer Instruction Mnemonics ---
     JMPL    , RESTORE , RETT     , SAVE    , CALL    ,
     BN      , BE      , BLE      , BL      , BLEU    ,
     BCS     , BNEG    , BVS      , BA      , BNE     ,
     BG      , BGE     , BGU      , BCC     , BPOS    ,
     BVC     , CBN     , CB123    , CB12    , CB13    ,
     CB1     , CB23    , CB2      , CB3     , CBA     ,
     CB0     , CB03    , CB02     , CB023   , CB01    ,
     CB013   , CB012   , FBN      , FBNE    , FBLG    ,
     FBUL    , FBL     , FBUG     , FBG     , FBU     ,
     FBA     , FBE     , FBUE     , FBGE    , FBUGE   ,
     FBLE    , FBULE   , FBO      , TN      , TE      ,
     TLE     , TL      , TLEU     , TCS     , TNEG    ,
     TVS     , TA      , TNE      , TG      , TGE     ,
     TGU     , TCC     , TPOS     , TVC     ,
        --- Read/Write Control Register Instruction Mnemonics ---
     RDPSR   , RDTBR   , RDWIM    , RDY     , WRPSR   ,
     WRTBR   , WRWIM   , WRY      ,
        --- Miscellaneous Instruction Mnemonics ---
     SETHI   , UNIMP   , FLUSH    , -- IFLUSH instead of FLUSH in SPARC v.7
     RDASR   , WRASR   , STBAR    , -- SPARC v.8 only
        --- Integer Multiply/Divide Instructions Mnemonics ---
                   --- SPARC Version 8 only ---
     UMUL    , UMULcc  , SMUL     , SMULcc   , UDIV   ,
     UDIVcc  , SDIV    , SDIVcc   ,
        --- Floating-Point Instruction Mnemonics ---
     FiTOs   , FiTOd   , FiTOq    , FsTOi    , FdTOi  ,
     FqTOi   , FsTOd   , FsTOq    , FdTOs    , FdTOq  ,
     FqTOs   , FqTOd   , FMOVs    , FNEGs    , FABSs  ,
     FSQRTs  , FSQRTd  , FSQRTq   , FADDs    , FADDd  ,
     FADDq   , FSUBs   , FSUBd    , FSUBq    , FMULs  ,
     FMULd   , FMULq   ,
     FsMULd  , FdMULq  , -- SPARC v.8 only for FsMULd & FdMULq
     FDIVs   , FDIVd   , FDIVq    , FCMPs    , FCMPd  ,
     FCMPq   , FCMPEs  , FCMPEd   , FCMPEq   ,
        --- Coprocessor Instruction Mnemonics ---
      CPop1  , CPop2    
  );


  -- Pseudo-functions to tell if an instruction mnemonic is an OPcc (IsOPcc)
  -- or a Bicc or a FBfcc or CBccc.
  -- Constants have deferred values.
  type IsOPccType is array(SuperInstMnemonic) of boolean;
  constant IsOPcc : IsOPccType;
  type IsBranchingInstType is array(SuperInstMnemonic) of boolean;
  constant IsBicc  : IsBranchingInstType;
  constant IsFBfcc : IsBranchingInstType;
  constant IsCBccc : IsBranchingInstType;
  
  -- Other pseudo-functions:
  -- IURs1Rs2AreIn(Mnemonic) returns TRUE if Mnemonic has a source register
  -- rs1 or rs2.
  -- FPURsIsIn(Mnemonic) returns TRUE if Mnemonic has a source register
  -- rs1.
  -- IsFPinst(Mnemonic) returns TRUE if Mnemonic is a FP instruction.
  -- IsFPop(Mnemonic) returns TRUE if Mnemonic is a FP operation.
  -- IsFCMP(Mnemonic) returns TRUE if Mnemonic is a FP compare.
  type MnemoTableType is array(SuperInstMnemonic) of boolean;
  constant IURs1Rs2AreIn : MnemoTableType;
  constant FPURs1IsIn    : MnemoTableType;
  constant IsFPinst      : MnemoTableType;
  constant IsFPop        : MnemoTableType;
  constant IsFPopDouble  : MnemoTableType;
  constant IsFPopQuad    : MnemoTableType;
  constant IsFCMP        : MnemoTableType;
  
  -- Other pseudo-functions for LOAD AND STORE instructions
  -- IsLoadDoubleInst(Mnemonic) returns TRUE if Mnemonic is a LOAD instruction
  -- for double words.
  -- IsLoadInst(Mnemonic) returns TRUE if Mnemonic is a LOAD instruction.
  -- IsLoadSingleInst(Mnemonic) returns TRUE if Mnemonic is a LOAD instruction
  -- for "single" words.
  -- IsLoadFP_CPInst(Mnemonic) returns TRUE if Mnemonic is a Floating-Point
  -- or Coprocessor LOAD.
  -- IsStoreInst(Mnemonic) returns TRUE if Mnemonic is a store instruction.
  -- and so on...
  constant IsLoadDoubleInst   : MnemoTableType;
  constant IsLoadInst         : MnemoTableType;
  constant IsLoadSingleInst   : MnemoTableType;
  constant IsLoadFP_CPInst    : MnemoTableType;
  constant IsLoadByteInst     : MnemoTableType;
  constant IsLoadHalfwordInst : MnemoTableType;
  constant IsLoadInstASI      : MnemoTableType;
  constant IsStoreInst        : MnemoTableType;
  constant IsStoreDoubleInst  : MnemoTableType;
  constant IsStoreFP_CPInst   : MnemoTableType;
  constant IsStoreInstASI     : MnemoTableType;
  constant IsStoreSingleInst  : MnemoTableType;
  
  type Instruction is record
     Mnemo       : SuperInstMnemonic; -- mnemonic of an instruction
     asi         : natural; -- address space identifier
     i           : natural; -- i bit
     a           : natural; -- annul bit for branch instructions
     rd          : natural; -- destination register
     rs1         : natural; -- source register 1
     rs2         : natural; -- source register 2
     simm13      : natural; -- 13-bit immediate value
     disp30      : std_logic_vector(29 downto 0); -- displacement for CALL
     disp22      : natural; -- 22-bit displacement for taken branches
                            -- or 22-bit constant for SETHI & UNIMP inst.
     
     Address     : std_logic_vector(31 downto 0); -- instruction address
     NextAddress : std_logic_vector(31 downto 0); -- addr. of the following
                                                  -- instruction
     Annul       : boolean; -- for branching instruction: TRUE if annulled
     BitInstr    : std_logic_vector(31 downto 0); -- 32-bit value of instr.
  end record; -- Instruction
  
  -- RegisterFile: unbounded array of 32-bit words.
  type RegisterFile is array(natural range <>) of std_logic_vector(31 downto 0);
  
  -- Declarations related to trap handling.
  type TrapMnemonic is (
     DETECTED_TRAP,   -- Used to set flag when a trap is detected (except for
                      -- reset traps).
     RESET_TRAP,      -- reset trap mnemo.
     INST_ACCESS,     -- instruction access exception trap
     ILLEGAL_INST,    -- illegal instruction trap
     PRIVILEGED_INST, -- privileged instruction trap
     FP_DISABLED,     -- Floating-Point disabled trap
     CP_DISABLED,     -- Coprocessor disabled trap
     WINDOW_OVERFLOW, -- window overflow trap
     WINDOW_UNDERFLOW, -- window underflow trap
     MEM_ADDR_NOT_ALIGNED, -- memory-address-not-aligned trap
     FP_EXCEPTION,    -- Floating-Point exception trap
     CP_EXCEPTION,    -- Coprocessor exception trap
     DATA_ACCESS_EXCEPTION, -- data access exception trap
     TAG_OVERFLOW,    -- tag overflow trap for TADDccTV & TSUBccTV
     TRAP_INST,       -- trap instruction Ticc
     INTERRUPT_LEVEL, -- interrupting trap with IRL(3:0)
     PROGRAM_FLOW_ERR, -- Program Flow Error (hardware trap).
     NON_RESTART_IMPRECISE, -- Non-restartable, imprecise error.
     RESTART_IMPRECISE -- Restartable, imprecise error
  );
  
  type TrapVectorType is array(TrapMnemonic) of boolean;
  type TrapType is array(TrapMnemonic) of std_logic_vector(7 downto 0);
  constant TrapTypeTable : TrapType := 
  (
    DETECTED_TRAP         => "00000000", -- no trap type here! Dummy constant!
    RESET_TRAP            => "00000000", -- same thing here (Dummy constant).
    INST_ACCESS           => "00000001", 
    ILLEGAL_INST          => "00000010",
    PRIVILEGED_INST       => "00000011",
    FP_DISABLED           => "00000100",
    CP_DISABLED           => "00100100",
    WINDOW_OVERFLOW       => "00000101",
    WINDOW_UNDERFLOW      => "00000110",
    MEM_ADDR_NOT_ALIGNED  => "00000111",
    FP_EXCEPTION          => "00001000",
    CP_EXCEPTION          => "00101000",
    DATA_ACCESS_EXCEPTION => "00001001",
    TAG_OVERFLOW          => "00001010",
    TRAP_INST             => "00000000", -- Dummy constant: trap type is 
                                         -- computed during execution of Ticc.
    INTERRUPT_LEVEL       => "00000000", -- Dummy constant: trap type is
                                         -- determined by concatenating 0001
                                         -- with IRL value: 0001 & IRL(3:0).
    PROGRAM_FLOW_ERR      => "01100110",
    NON_RESTART_IMPRECISE => "01100100",
    RESTART_IMPRECISE     => "01100011"