def.h

image capture billing control system

//#define	VERSION	0x0010	//0.10
#define	VERSION	0x0090	//0.90

typedef	bit		Bit;
typedef	bit		Bool;
typedef	unsigned char	Byte;
typedef	unsigned int	Word;
typedef	unsigned long	Dword;
typedef	code		RDATA;

#define	dByte		Byte data
#define	dWord		Word data
#define	xWord		Word xdata
#define	xByte		Byte xdata
#define	iByte		Byte idata

#define	TRUE		1
#define	FALSE		0
#define	HIGH		1
#define	LOW			0

#define	IDE_READ	0
#define	IDE_WRITE	1

sfr	MutiControl1	= 0xFD;	// MP3 Control Register
sfr	MutiControl2	= 0xB1;
sfr	LptDataIn	= 0xB2;

sfr	XRAMP		= 0xFA;	// Aux RAM high byte address
//---- IDE SFR -------------------------------------------------------------
sfr	CF_Control	= 0xC0; // IDE control register (bit addressing)
sfr	CF_Data		= 0xDA; //  W IDE data register, trigger
sfr	CF_Feature	= 0xD1; //  W IDE feature register
sfr	CF_Error	= 0xD1; // R  IDE error register
sfr	CF_SectorCount	= 0xD2; // RW IDE sector counter register

sfr	CF_SectorNumber	= 0xD3; // RW IDE sector number register
sfr	CF_LBA_7_0	= 0xD3; // RW
sfr	CF_CylinderLow	= 0xD4; // RW IDE cylinder low register
sfr	CF_LBA_15_8	= 0xD4; // RW
sfr	CF_CylinderHigh	= 0xD5; // RW IDE cylinder high register
sfr	CF_LBA_23_16	= 0xD5; // RW
sfr	CF_DriveHead	= 0xD6; // RW IDE drive head register
sfr	CF_Command	= 0xD7; //  W IDE command register
sfr	CF_Status	= 0xD7; // R  IDE status register
sfr	CF_DeviceControl= 0xD9; //  W IDE device control register
sfr	CF_AltStatus	= 0xD9; // R  IDE alt status register
sfr	CF_Trigger	= 0xD8; // IDE transaction start (bit addressing)

//	CF_CONTROL	= 0xC0; // IDE control register (bit addressing)
sbit	cf_iordy	= 0xC0; // R  from input pin
sbit	cf_card_detect	= 0xC1; // R  0:have card  ,  1:no card
sbit	cf_card_remove	= 0xC2; // R  set when card remove, clear when uP read
sbit	cf_irq		= 0xC3; // R  IDE interrupt request, clear when uP read
sbit	cf_direction	= 0xC4; // RW Data transfer direction, 0:read, 1:write
sbit	cf_card_select	= 0xC5; // RW 0:IDE interface, 1:Smart Media card
sbit	cf_sfr_ready	= 0xC6; // R  Read/Write SFR, 1:Ready, 0:busy
sbit	cf_reset	= 0xC7; // RW IDE interface reset, active high

//	CF_TRIGGER	= 0xD8; // IDE transaction start (bit addressing)
sbit	cf_3f6_tri	= 0xD8; // RW Device Control / Alt Status trigger
sbit	cf_1f7_tri	= 0xD9; // R  Command / Status trigger
sbit	cf_1f6_tri	= 0xDA; // RW Drive Head trigger
sbit	cf_1f5_tri	= 0xDB; // RW Cylinder High trigger
sbit	cf_1f4_tri	= 0xDC; // R  Cylinder Low trigger
sbit	cf_1f3_tri	= 0xDD; // R  Sector Number trigger
sbit	cf_1f2_tri	= 0xDE; // R  Sector Count trigger
sbit	cf_1f1_tri	= 0xDF; // R  feature / error transaction start

//---- MMU SFR -------------------------------------------------------------
sfr   MMU_Control	= 0xC8; // MMU Control Register (bit addressing)
sfr   MMU_51Addr	= 0xFC; // 8051 used buffer ADDRL pointer register
sfr   MMU_CardAddr	= 0xFB; // Card used buffer ADDRL pointer register
sfr   MMU_AddrHigh	= 0xF8; // Sector buffer ADDRH pointer register
sfr   MMU_Data		= 0xF9; // 8051 R/W sector buffer DATA register

//    MMU_CONTROL	= 0xC8; // MMU Control Register (bit addressing)
sbit  mmu_reset		= 0xC8; // RW Software reset MMU
sbit  mmu_8051		= 0xC9; // RW 8051 control sector buffer
sbit  mmu_swappable	= 0xCA; // R  Both of sector buffer are available

//---- SMI SFR -------------------------------------------------------------
sfr   SMI_MakerCode	=  0xD1; // R  Flash Maker Code Register
sfr   SMI_DeviceCode	=  0xD2; // R  Flash Device Code Register
sfr   SMI_Status	=  0xD3; // R  SmartMedia Card Status Register
sfr   SMI_Command	=  0xD4; // R  SmartMedia Card Command Register
sfr   SMI_Address0	=  0xD5; // RW SmartMedia Card Address 0 Register
sfr   SMI_Address1	=  0xD6; // RW SmartMedia Card Address 1 Register
sfr   SMI_Address2	=  0xD7; // RW SmartMedia Card Address 2 Register
sfr   SMI_Address3	=  0xD9; // RW SmartMedia Card Address 3 Register
sfr   SMI_Control	=  0x98; // RW SmartMedia Control Register
sfr   SMI_Trigger	=  0xD8; // RW Flash Auto-Function Trigger Register

//    SMI_Trigger		=  0xD8; // RW Flash Auto-Function Trigger Register
sbit  smi_t_id			=  0xD8; // 0 01
sbit  smi_t_status		=  0xD9; // 1 02
sbit  smi_t_command	=  0xDA; // 2 04
sbit  smi_ecc_page		=  0xDB; // 3 08
sbit  smi_t_command_address	=  0xDC; // 4 10
sbit  smi_t_data		=  0xDD; // 5 20
sbit  smi_ecc_enable		=  0xDE; // 6 40
sbit  smi_xfer_dir		=  0xDF; // 7 80

//	SMI_Control		=  0x98; // RW SmartMedia Control Register
sbit  smi_ready			=  0x98; // 0 01 R
sbit  smi_64_128m			=  0x99; // 1 02
sbit  smi_erase_enable		=  0x9A; // 2 04
sbit  smi_ecc_done			=  0x9B; // 3 08 R
sbit  smi_ecc_256b			=  0x9C; // 4 10
sbit  smi_write_protect	=  0x9D; // 5 20
sbit  smi_card_enable		=  0x9E; // 6 40
sbit  smi_reset			=  0x9F; // 7 80


//	USB 
sfr	USBI_CMD		= 0xBD;	// Control endpoint data register
sfr	USBI_CX			= 0xC1;	// Control endpoint control register
sfr	USBI_INTR		= 0xEC;	// Interrupt endpoint data rate register
sfr	USBI_CR			= 0xAB;	// Interrupt endpoint control register
sfr	USBI_CRD1		= 0xAC;	// Interrupt endpoint data register 1
sfr	USBI_CRD2		= 0xAD;	// Interrupt endpoint data register 2
sfr	USBI_CRD3		= 0xAE;	// Interrupt endpoint data register 3
sfr	USBI_CRD4		= 0xAF;	// Interrupt endpoint data register 4
sfr	USBI_CRD5		= 0xB9;	// Interrupt endpoint data register 5
sfr	USBI_CRD6		= 0xBA;	// Interrupt endpoint data register 6
sfr	USBI_CRD7		= 0xBB;	// Interrupt endpoint data register 7
sfr	USBI_CRD8		= 0xBC;	// Interrupt endpoint data register 8
sfr	USBI_BULK		= 0xAA;	// Bulk In/Out endpoint control register
sfr	USBI_INT		= 0xA9;	// USB interrupt control register
sfr	USBI_GEN		= 0xEA;	// USB general control register
sfr	USBI_VID1		= 0xC2;	// USB Vender ID register Low
sfr	USBI_VID2		= 0xC3;	// USB Vender ID register High
sfr	USBI_PID1		= 0xC4;	// USB Product ID register Low
sfr	USBI_PID2		= 0xC5;	// USB Product ID register High
sfr	USBI_DEV1		= 0xC6;	// USB Device release number register Low
sfr	USBI_DEV2		= 0xC7;	// USB Device release number register High
sfr	USBI_PWR		= 0xEC;	// USB Power source configuration register
sfr	USBI_MPW		= 0xED;	// USB Maximum power source consumption register

#define Bulk_Complete	!(USBI_BULK & 0x02)


//---- Port0 - 3 -------------------------------------------------------
sfr	P0CfgA	= 0x84;		//	Port Mode	PnCfgB	PnCfgA
sfr	P0CfgB	= 0x86;		//	Open Drain	0	0
sfr	P1CfgA	= 0x9E;		//	Quasi		0	1
sfr	P1CfgB	= 0x9F;		//	High Impedence	1	0
sfr	P2CfgA	= 0xA4;		//	Push Pull	1	1
sfr	P2CfgB	= 0xA5;		//
sfr	P3CfgA	= 0xBE;		//
sfr	P3CfgB	= 0xBF;

sbit	P00	= 0x80;
sbit	P01	= 0x81;
sbit	P02	= 0x82;
sbit	P03	= 0x83;
sbit	P04	= 0x84;
sbit	P05	= 0x85;
sbit	P06	= 0x86;
sbit	P07	= 0x87;

sbit	P10	= 0x90;
sbit	P11	= 0x91;
sbit	P12	= 0x92;
sbit	P13	= 0x93;
sbit	P14	= 0x94;
sbit	P15	= 0x95;
sbit	P16	= 0x96;
sbit	P17	= 0x97;
/*
sbit	nLed = 0x90;			// P10
sbit	KeyScan = 0x93			// P13
sbit	DecoderReset = 0x95;	// P15
sbit	IicData = 0x96;			// P16
sbit	IicClk	= 0x97;			// P17
*/
sbit	P20	= 0xA0;
sbit	P21	= 0xA1;
sbit	P22	= 0xA2;
sbit	P23	= 0xA3;
sbit	P24	= 0xA4;
sbit	P25	= 0xA5;
sbit	P26	= 0xA6;
sbit	P27	= 0xA7;

sbit	P30	= 0xB0;
sbit	P31	= 0xB1;
sbit	P32	= 0xB2;
sbit	P33	= 0xB3;
sbit	P34	= 0xB4;
sbit	P35	= 0xB5;
sbit	P36	= 0xB6;
sbit	P37	= 0xB7;

#define	Red_On()		P10=1
#define	Red_Off()		P10=0

#define	Green_On()		P11=1
#define	Green_Off()		P11=0

//-------

//#define	REAL_BOARD		1	// 0: test board	1: real board

//#if REAL_BOARD

//#define	KeyScan			P34
#define	VDD_On()		P12=1
#define	VDD_Off()		P12=0

#define	PUP_Check		P13

#define	WSEN_On()		P14=1
#define	WSEN_Off()		P14=0

#define	DCEN_Check		P15
#define	DCEN_On()		P15=1
#define	DCEN_Off()		P15=0
/*
#else

#define	KeyScan			P13
#define	DAC_On()		P15=1
#define	DAC_Off()		P15=0

#endif*/
//--------------------------
#define	IicData			P16
#define	IicClk			P17

/*
#define	ADC_On()	P30=0
#define	ADC_Off()	P30=1
#define	ADC_In		P31
*/
#define	BAT_Check	P30
#define	USB_Reset	P31

#define	Freq_Ctrl	P34
#define	Freq_12M()	P34=1
#define	Freq_24M()	P34=0

#define	USB_Connected	P35

/*
#define	Freq_6M()	P34=0	; P35=1
#define	Freq_12M()	P34=1	; P35=0
#define	Freq_24M()	P34=0	; P35=0
*/
/*
sbit	LptDataOut	= 0x90;		// P10
sbit	LptAck		= 0x91;		// P11
sbit	LptReq		= 0x92;		// P12
sbit	LptDisable	= 0x93;		// P13
*/
//sbit	PowerOnPin	= 0x94;		// P14

//---- MMU macro -----------------------------------------------------------
#define	SectorBuffer51Mode()	mmu_8051 = 1;	// 8051 control sector buffer
#define	SectorBufferCardMode()	mmu_8051 = 0;	// direct memory access

#define	DMA_Mode_On()			mmu_8051 = 0
#define	DMA_Mode_Off()			mmu_8051 = 1

/*
#define	SectorBufferForUSB()	MutiControl2 &= 0xF9;	// USB -> Flash Mem
#define	SectorBufferForMP3()	MutiControl2 = (MutiControl2 & 0xF9) | 0x02;	// Flash Mem -> Decoder
#define	SectorBufferForLPT()	MutiControl2 = (MutiControl2 & 0xF9) | 0x04;	// LPT -> Flase Mem
*/
#define	SectorBufferForUSB()	MutiControl2 = 0x00;	// USB -> Flash Mem
#define	SectorBufferForMP3()	MutiControl2 = 0x02;	// Flash Mem -> Decoder
#define	USB_Mode()				MutiControl2 = 0x00;	// USB -> Flash Mem
#define	MP3_Mode()				MutiControl2 = 0x02;	// Flash Mem -> Decoder
//#define	SectorBufferForLPT()	MutiControl2 = (MutiControl2 & 0xF9) | 0x04;	// LPT -> Flase Mem
//#define	TriggerLPT()		MutiControl2 |= 0x01;	// LPT function enable

//#define	ResetMMU()			mmu_reset = 1;		mmu_reset = 0;
#define	MMU_Reset()			{ mmu_reset = 1;		mmu_reset = 0; }
//#define	WriteMMU(x)			MMU_Data = x;
#define	MMU_51(xh,xl)		{ mmu_8051 = 1;	MMU_51Addr = xl;	MMU_AddrHigh = xh; }
#define	MMU_Normal(xh,xl)	{ mmu_8051 = 0;	MMU_CardAddr = xl;	MMU_AddrHigh = xh; }

#define	Select_SMC()	   	MutiControl1 =  MutiControl1 & 0xF9;
#define	Select_Mem1()		MutiControl1 = (MutiControl1 & 0xF9) | 0x02;
#define	Select_Mem2()		MutiControl1 = (MutiControl1 & 0xF9) | 0x04;
#define	Trigger_MP3()		MutiControl1 |= 0x01;	// MP3 function enable
#define	MP3_Enable()		MutiControl1 |= 0x01;	// MP3 function enable
#define	MP3_Disable()		MutiControl1 &= 0xfe;	// MP3 function disable

#define	DOWNLOAD_REQ	0x0A
#define	UPLOAD_REQ		0x0B
#define	Trigger_Download()	USBI_BULK = DOWNLOAD_REQ
#define	Trigger_Upload()	USBI_BULK = UPLOAD_REQ
//#define	USB_Connected		(USBI_GEN&0x01)