dec2812.map.rpt

DSP2812开发板板上的CPLD源代码

;     -- Register only                        ; 30    ;
;     -- Combinational with a register        ; 0     ;
;                                             ;       ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 21    ;
;     -- 3 input functions                    ; 16    ;
;     -- 2 input functions                    ; 6     ;
;     -- 1 input functions                    ; 0     ;
;     -- 0 input functions                    ; 0     ;
;         -- Combinational cells for routing  ; 0     ;
;                                             ;       ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 73    ;
;     -- arithmetic mode                      ; 0     ;
;     -- qfbk mode                            ; 0     ;
;     -- register cascade mode                ; 0     ;
;     -- synchronous clear/load mode          ; 0     ;
;     -- asynchronous clear/load mode         ; 0     ;
;                                             ;       ;
; Total registers                             ; 30    ;
; I/O pins                                    ; 72    ;
; Maximum fan-out node                        ; A[9]  ;
; Maximum fan-out                             ; 17    ;
; Total fan-out                               ; 257   ;
; Average fan-out                             ; 1.77  ;
+---------------------------------------------+-------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                     ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name   ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------+
; |DEC2812                   ; 73 (25)     ; 30           ; 0          ; 72   ; 0            ; 43 (25)      ; 30 (0)            ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |DEC2812              ;
;    |74138:inst10|          ; 4 (4)       ; 0            ; 0          ; 0    ; 0            ; 4 (4)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |DEC2812|74138:inst10 ;
;    |74244:inst12|          ; 3 (3)       ; 0            ; 0          ; 0    ; 0            ; 3 (3)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |DEC2812|74244:inst12 ;
;    |74244:inst13|          ; 11 (11)     ; 0            ; 0          ; 0    ; 0            ; 11 (11)      ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |DEC2812|74244:inst13 ;
;    |74273:inst11|          ; 1 (1)       ; 1            ; 0          ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |DEC2812|74273:inst11 ;
;    |74273:inst1|           ; 8 (8)       ; 8            ; 0          ; 0    ; 0            ; 0 (0)        ; 8 (8)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |DEC2812|74273:inst1  ;
;    |74273:inst22|          ; 3 (3)       ; 3            ; 0          ; 0    ; 0            ; 0 (0)        ; 3 (3)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |DEC2812|74273:inst22 ;
;    |74273:inst2|           ; 7 (7)       ; 7            ; 0          ; 0    ; 0            ; 0 (0)        ; 7 (7)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |DEC2812|74273:inst2  ;
;    |74273:inst7|           ; 3 (3)       ; 3            ; 0          ; 0    ; 0            ; 0 (0)        ; 3 (3)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |DEC2812|74273:inst7  ;
;    |74273:inst|            ; 8 (8)       ; 8            ; 0          ; 0    ; 0            ; 0 (0)        ; 8 (8)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |DEC2812|74273:inst   ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 30    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in D:/2812board_N/DEC2812.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Thu Jul 26 16:59:40 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off DEC2812 -c DEC2812
Info: Found 1 design units, including 1 entities, in source file DEC2812.bdf
    Info: Found entity 1: DEC2812
Info: Elaborating entity "DEC2812" for the top level hierarchy
Warning: Block or symbol "NOT" of instance "inst24" overlaps another block or symbol
Warning: Block or symbol "NOT" of instance "inst32" overlaps another block or symbol
Warning: Block or symbol "NOT" of instance "inst52" overlaps another block or symbol
Warning: Port "D8" of type 74273 and instance "inst2" is missing source signal
Warning: Port "D2" of type 74273 and instance "inst11" is missing source signal
Warning: Port "D3" of type 74273 and instance "inst11" is missing source signal
Warning: Port "D4" of type 74273 and instance "inst11" is missing source signal
Warning: Port "D7" of type 74273 and instance "inst11" is missing source signal
Warning: Port "D6" of type 74273 and instance "inst11" is missing source signal
Warning: Port "D5" of type 74273 and instance "inst11" is missing source signal
Warning: Port "D8" of type 74273 and instance "inst11" is missing source signal
Warning: Port "D4" of type 74273 and instance "inst7" is missing source signal
Warning: Port "D7" of type 74273 and instance "inst7" is missing source signal
Warning: Port "D6" of type 74273 and instance "inst7" is missing source signal
Warning: Port "D5" of type 74273 and instance "inst7" is missing source signal
Warning: Port "D8" of type 74273 and instance "inst7" is missing source signal
Warning: Port "D4" of type 74273 and instance "inst22" is missing source signal
Warning: Port "D7" of type 74273 and instance "inst22" is missing source signal
Warning: Port "D6" of type 74273 and instance "inst22" is missing source signal
Warning: Port "D5" of type 74273 and instance "inst22" is missing source signal
Warning: Port "D8" of type 74273 and instance "inst22" is missing source signal
Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus51/libraries/others/maxplus2/74273.bdf
    Info: Found entity 1: 74273
Info: Elaborating entity "74273" for hierarchy "74273:inst2"
Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus51/libraries/others/maxplus2/74244.bdf
    Info: Found entity 1: 74244
Info: Elaborating entity "74244" for hierarchy "74244:inst4"
Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus51/libraries/others/maxplus2/74138.bdf
    Info: Found entity 1: 74138
Info: Elaborating entity "74138" for hierarchy "74138:inst10"
Warning: Converted TRI buffer or tri-state bus to logic, or removed OPNDRN
    Warning: Converting TRI node "74244:inst4|26" that feeds logic to a wire
    Warning: Converting TRI node "74244:inst4|27" that feeds logic to a wire
    Warning: Converting TRI node "74244:inst4|31" that feeds logic to a wire
    Warning: Converting TRI node "74244:inst4|36" that feeds logic to a wire
    Warning: Converting TRI node "74244:inst4|1" that feeds logic to a wire
    Warning: Converting TRI node "74244:inst4|6" that feeds logic to a wire
    Warning: Converting TRI node "74244:inst4|10" that feeds logic to a wire
    Warning: Converting TRI node "74244:inst4|11" that feeds logic to a wire
Info: Implemented 145 device resources after synthesis - the final resource count might be different
    Info: Implemented 27 input pins
    Info: Implemented 37 output pins
    Info: Implemented 8 bidirectional pins
    Info: Implemented 73 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 30 warnings
    Info: Processing ended: Thu Jul 26 16:59:42 2007
    Info: Elapsed time: 00:00:03